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hynix semiconductor inc. 8-bit single-chip microcontrollers gms81c5108 users manual (ver. 1.0)
version 1.0 published by mcu application team 20 20 20 200 0 0 01 1 1 1 hynix semiconductor inc. all rights reserved. additional information of this manual may be served by hynix semiconductor offices in korea or distributors and repre- sentatives listed at address directory. hynix semiconductor reserves the right to make changes to any information here in at any time without notice. the information, diagrams and other data in this manual are correct and reliable; however, hynix semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
gms81c5108 june 2001 ver 1.0 table of contents 1. overview ...........................................1 description .........................................................1 features .............................................................1 development tools ............................................2 ordering information 2. block diagram ................................3 3. pin assignment ...............................4 4. package diagram ...........................5 5. pin function .....................................6 6. port structures ...........................8 7. electrical characteristics ...11 absolute maximum ratings .............................11 recommended operating conditions ..............11 dc electrical characteristics ...........................12 lcd characteristics .........................................13 a/d converter characteristics .........................13 ac characteristics ...........................................14 serial i/o characteristics .................................15 typical characteristics..................................... 16 8. memory organization ................18 registers ..........................................................18 program memory .............................................21 data memory ................................................... 24 addressing mode ............................................. 27 9. i/o ports ..........................................31 registers for port .............................................31 i/o ports configuration ....................................32 10. clock generator ......................34 operation mode ...............................................36 operation mode switching ...............................37 power saving operation .......................39 11. basic interval timer .................43 12. timer / counter .................................45 8-bit timer/counter mode ................................48 16 bit timer/counter mode ..............................50 8-bit capture mode ......................................... 50 16-bit capture mode ....................................... 53 8-bit (16-bit) compare output mode .............. 53 pwm mode ..................................................... 53 13. watch timer/watch dog timer......... 56 watch timer .................................................... 56 watch dog timer ............................................ 57 14. analog to digital converter ..............58 15. buzzer output function ....................60 16. serial communication interface ........62 data transmit/receive timing........................ 63 the method of serial i/o ................................. 64 17. interrupts ...................................65 interrupt sequence .......................................... 66 brk interrupt .................................................. 68 multi interrupt .................................................. 68 external interrupt ............................................. 69 18. key scan ........................................70 19. lcd driver .................................... 71 configuration of lcd driver ............................. 71 control of lcd driver circuit ........................... 72 lcd display memory ...................................... 73 control method of lcd driver ......................... 74 20. remocon carrier generator ............. 76 remocon signal output control ..................... 76 carrier frequency ........................................... 77 21. oscillator circuit ....................80 22. reset ..............................................81 external reset input ........................................ 81 watchdog timer reset ................................... 81 23. supply voltage detection ....82 24. devemopment tools .................83 otp programming .......................................... 83 emulator s/w setting ...................................... 84 a. control register list ................. i b. instruction .................................... iii terminology list................................................ iii instruction map ..................................................iv instruction set ....................................................v c. mask order sheet ....................... xi
gms81c5108 june 2001 ver 1.0 1 gms81c5108 cmos single-chip 8-bit microcontroller with lcd controller/driver and infrared remote control transmitters 1. overview 1.1 description the gms81c5108 is an advanced cmos 8-bit microcontroller with 8k bytes of rom. the device is one of gms800 fam- ily. the hynix gms81c5108 is a powerful microcontroller which provides a high flexibility and cost effective solution to many lcd applications. the gms81c5108 provides the following standard features: 8k bytes of rom, 192 bytes of ram, 37 nibbles of display ram, 8/16-bit timer/counter, on-chip oscillator and clock circuitry. in addition, the gms81c5108 supports power saving modes to reduce power consumption. this document is only explained for the base of gms81c5108, the eliminated functions are same as below. 1.2 features ? 8k bytes of on-chip program memory ? 192 bytes of on-chip data ram ? 37 nibbles of display ram ? instruction cycle time: - 1us at 4mhz (2 cycle nop instruction) ? 24 programmable i/o pins ? 2v to 4v operating range ? dual clock operation - main : 400khz ~ 4.2mhz - sub. : 32.768khz ? one 8-bit basic interval timer/counter ? key scan interrupt ? two 8-bit timer/ counter (it can be used one 16-bit timer/counter) ? watch timer (2hz, 4hz, 16hz, 1/64hz) ? 8-bit serial i/o (sio) ? one 10-bit high speed pwm output ? carrier generator for remote controller ? 11 interrupt sources - 3 external interrupts (int0 ~ 2) - 8 internal interrupts (bit, timer 2, wt, a/dc, sio, rem, keyscan) ? 6-bit buzzer driving port - 500hz ~ 250khz (@4mhz) ? 4-channel 8-bit on-chip a/d converter ? power saving mode - stop, sleep, sub active mode ? lcd display/controller (lcdc) - static mode (37seg 1com, 1/3 bias) - 1/2 duty mode (36seg 2com, 1/3 bias) - 1/3 duty mode (35seg 3com, 1/3 bias) - 1/4 duty mode (34seg 4com, 1/3 bias) ? lcd display voltage booster ? supply voltage detector(svd) - 2 level detector (2.2v, 1.7v) device name rom size otp size ram size i/o package gms81c5108 8k bytes - 192 bytes 24 80qfp gms87c5108 8k bytes 192bytes 24 80qfp
gms81c5108 2 june 2001 ver 1.0 1.3 development tools note: there are several setting switches in the emulator. user should read carefully and do setting properly before developing the program refer to "24.2 emulator s/w set- ting" on page 84. otherwise, the emulator may not work properly. the gms81c5108 is supported by a full-featured macro assem- bler, an in-circuit emulator choice-dr. tm and otp program- mers. there are two different type programmers such as single type and gang type. for mode detail, refer to otp programming chapter. macro assembler operates under the ms-windows 95/ 98 tm . please contact sales part of hynix semiconductor. 1.4 ordering information software - ms- window base assembler - linker / editor / debugger hardware (emulator) - choice-dr. - choice-dr. eva 81c51 b/d otp writer - choice - sigma (single writer) - choice - gang4 (gang writer) device name rom size (bytes) ram size package mask rom version gms81c5108 8k bytes 192 bytes 80qfp otp rom version gms87c5108 8k bytes otp 192 bytes 80qfp
gms81c5108 june 2001 ver 1.0 3 2. block diagram alu lcd controller/driver (lcdc) accumulator stack pointer interrupt controller data memory lcd memory display program memory data table pc 8-bit basic interval tim er high speed pc r1 r0 r3 buzzer driver psw system controller timing generator system clock controller clock generator high freq. low freq. reset x in x out sx in sx out segment drive output seg0 ~ seg33 common drive output com0 r00 / int0 r01 / int1 r02 / int2 r03 / ec0 r04 / buz r05 / sck r06 / so r07 / si r10 / ks0 r11 / ks1 r12 / ks2 r13 / ks3 r14 / ks4 r15 / ks5 r16 / ks6 r17 / ks7 r30 v dd v ss power supply vcl0 vcl1 vcl2 com1/seg36 com2/seg35 com3/seg34 lcd display voltage booster caph capl vlcdc av dd av ss power supply circuit vreg r20 / an0 r31 / pwm r32 r33 r21 / an1 r22 / an2 r23 / an3 8-bit a/d converter r2 pwm 8/16-bit timer/counter sio watch/watch dog timer wdtout remocon (rem) remout
gms81c5108 4 june 2001 ver 1.0 3. pin assignment av ss r23 / an3 r22 / an2 r21 / an1 r20 / an0 av dd seg0 vss seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 reset vreg wdtout sx in sx out vcl0 vlcdc vcl1 vcl2 caph capl com0 seg36 / com1 seg35 / com2 seg34 / com3 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 x out x in v dd remout r07 / si r06 / s0 r05 / sck r04 / buz r03 / ec0 r02 / int2 r01 / int1 r33 r32 r31 / pwm r30 r17 / ks7 r16 / ks6 r15 / ks5 r14 / ks4 r13 / ks3 r12 / ks2 r11 / ks1 r10 / ks0 r00 / int0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 gms81c5108
gms81c5108 june 2001 ver 1.0 5 4. package diagram figure 4-1 package diagram 20.10 19.90 24.15 23.65 18.15 17.65 14.10 13.90 3.10 max. 0.45 0.30 0.8 bsc see detail "a" 1.03 0.73 0-7 0.36 0.10 0.23 0.13 1.95 ref detail a unit: mm max min ----------- -
gms81c5108 6 june 2001 ver 1.0 5. pin function v dd : supply voltage. v ss : circuit ground. av dd : supply voltage to the ladder resistor of adc cir- cuit. to enhance the resolution of analog to digital convert- er, use independent power source as well as possible, other than digital power source. av ss : adc circuit ground reset : reset the mcu. wdtout : output for detection of a program malfunc- tion. if the user wants to use this pin, connect it to the re- set pin. remout: signal output of an infrared remote controller. x in : input to the inverting oscillator amplifier and input to the internal main clock operating circuit. x out : output from the inverting oscillator amplifier. sx in : input to the internal sub system clock operating cir- cuit. sx out : output from the inverting subsystem oscillator amplifier. seg0~seg36: segment signal output pins for the lcd display. see "19. lcd driver" on page 71 for details. com0~com3: common signal output pins for the lcd display. see "19. lcd driver" on page 71 for details. seg34~seg36 and com1~com3 are selected by lcdd of the lcr register. r00~r07: r0 is an 8-bit cmos bidirectional i/o port. r0 pins 1 or 0 written to the port direction register can be used as outputs or inputs. also, pull-up resistors and open- drain outputs can be assigned by software. in addition, r0 serves the functions of the various follow- ing special features. r10~r17: r1 is an 8-bit cmos bidirectional i/o port. r1 pins 1 or 0 written to the port direction register can be used as outputs or inputs or schmitt trigger inputs. also, pull- up resistors and open-drain outputs can be assigned by software. in addition, r1 serves the functions of the various follow- ing special features. r20~r23: r2 is a 4-bit cmos bidirectional i/o port. each pins 1 or 0 written to the port direction register can be used as outputs or inputs. also, pull-up resistors and open- drain outputs can be assigned by software. in addition, r2 serves the functions of the various follow- ing special features . r30~r33: r3 is a 4-bit cmos bidirectional i/o port. each pins 1 or 0 written to the port direction register can be used as outputs or inputs. also, pull-up resistors and open- drain outputs can be assigned by software. in addition, r3 serves the functions of the various follow- ing special features . vcl0~vcl2: power supply pins for the lcd driver. the voltage on each pin is vcl2 > vcl1 > vcl0. see "19. lcd driver" on page 71 for details. vlcdc: lcd drive voltage booster reference. caph, capl: lcd drive voltage booster capacitor. vreg: output of the voltage regular for the sub clock os- cillation circuit. connect external 0.1uf capacitor to this pin when using the sub system clock. port pin alternate function r00 r01 r02 r03 r04 r05 r06 r07 int0 (external interrupt 0) int1 (external interrupt 1) int2 (external interrupt 2) event counter input buzzer output sck (spi clk input/output) so (spi serial data output) si (spi serial data input) port pin alternate function r10 r11 r12 r13 r14 r15 r16 r17 ks0 (key scan input 0) ks1 (key scan input 1) ks2 (key scan input 2) ks3 (key scan input 3) ks4 (key scan input 4) ks5 (key scan input 5) ks6 (key scan input 6) ks7 (key scan input 7) port pin alternate function r20 r21 r22 r23 an0 (analog input port0) an1 (analog input port1) an2 (analog input port2) an3 (analog input port3) port pin alternate function r31 pwm (pwm output)
gms81c5108 june 2001 ver 1.0 7 pin name pin no. primary function secondary function state @ reset state @ stop i/o description i/o description v dd 62 - supply voltage - - - - v ss 33 - circuit ground - - - - av dd 35 - supply voltage for adc -- - - av ss 40 - ground for adc - - - - reset 65 i reset (low active) - - l input h input wdtout 67 o watch dog output - - floating (to be connect pull-up) state of before stop remout 61 o remocon output - - l output x in, x out 63, 64 i,o main clock oscillator - - oscillation l, l sx in, sx out 68, 69 i,o sub clock oscillator - - oscillation v reg 66 - sub clock voltage - - - - vcl0~vcl2 70,72,73 - lcd drive voltage - - internal vcl0 connected state of before stop vlcdc 71 - lcd drive voltage booster reference -- - - caph,capl 74,75 - lcd drive voltage booster capacitor -- internal vcl0 connected state of before stop seg0 ~ seg33 34, 32~1 o lcd segment output - - segment output com0 76 o lcd common output - - common output seg34/com3 seg35/com2 seg36/com1 79~77 o lcd common output. - lcd segment output common output state of before stop r00/int0 41 i/o general i/o port i interrupt input input port r01/int1 54 i/o i interrupt input r02/int2 55 i/o i interrupt input r03/ec0 56 i/o i event counter input r04/buz 57 i/o o buzzer output r05/sck 58 i/o i/o serial clock i/o r06/so 59 i/o o serial data output r07/si 60 i/o i serial data input r10 ~ r17/ ks0 ~ ks7 42~49 i/o i key wake-up input r20 ~ r23/ an0 ~ an3 36~39 i/o i a/d converter analog input r30,r32,r33 50,52,53 i/o - - r31/pwm 51 i/o o pwm output table 5-1 port function description
gms81c5108 8 june 2001 ver 1.0 6. port structures r00~r03/int0~int2, r03/ec0, r07/si r04/buz, r06/so r05/sck r10~r17/ks0~ks7 r20~r23/an0~an3 pin data reg. dir. reg. noise canceller int0 ~ int2 pull up reg. mux rd v dd v ss pull-up tr. ec0,si open drain reg. rd data bus pmr<0:3,7> pin data reg. dir. reg. pull up reg. mux rd v dd v ss pull-up tr. open drain reg. buz,so rd data bus pin data reg. dir. reg. pull up reg. mux rd v dd v ss pull-up tr. open drain reg. sck(out) noise canceller sck(in) rd data bus sck(in)_en pin data reg. dir. reg. pull up reg. mux rd v dd v ss pull-up tr. open drain reg. key scan key scan enable ks0 ~ ks7 noise canceller rd data bus ksmr<0:7> pin data reg. dir. reg. pull up reg. mux rd v dd v ss pull-up tr. open drain reg. a/d converter an0 ~ an3 a/d enable channel select rd data bus
gms81c5108 june 2001 ver 1.0 9 r30, r32, r33 r31 seg0 ~ seg33 com0 com1/seg36, com2/seg35, com3/seg34 vcl0 ~ vcl2, caph, capl vlcdc, vreg pin data reg. dir. reg. pull up reg. mux rd v dd v ss pull-up tr. open drain reg. rd data bus pin data reg. dir. reg. pull up reg. mux rd v dd v ss pull-up tr. open drain reg. pwmo rd data bus pin lcd data db vcl2 or vcl1 vcl1 or v ss lcd control reg. frame counter vcl2 pin vcl2 or vcl1 vcl1 or v ss lcd control frame counter vcl2 pin lcd data db vcl2 or vcl1 vcl1 or v ss lcd control reg. frame counter vcl2 pin vcl0 ~ vcl2, caph, capl pin v dd vcldc, vreg
gms81c5108 10 june 2001 ver 1.0 remout reset wdtout x in , x out (crystal or ceramic resonator option) x in , x out (rc option) sx in , sx out pin vdd vdd remout reset v ss noise canceller gms87c5108 (otp) internal reset reset v dd v ss noise canceller v dd mask option default no pull-up internal reset gms81c5108 (mask) pin wdtout wdtouten stop x out x in v dd v ss v dd v ss v dd main frequency clock x out x in v dd v ss v dd v ss v dd stop main frequency clock rc oscillator internal cap. = 5.0pf sx in sx out v ss v dd v ss v dd v dd v ss sub clock
gms81c5108 june 2001 ver 1.0 11 7. electrical characteristics 7.1 absolute maximum ratings supply voltage ........................................... -0.3 to +7.0 v storage temperature ................................-40 to +125 c voltage on any pin with respect to ground (v ss ) ............................................................... -0.3 to v dd +0.3 maximum current sunk by (i ol per i/o pin) ........20 ma maximum output current sourced by (i oh per i/o pin) ...............................................................................15 ma maximum current ( s i ol ) ....................................100 ma maximum current ( s i oh )...................................... 60 ma note: stresses above those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. 7.2 recommended operating conditions parameter symbol condition specifications unit min. typ. max. supply voltage v dd f main =4mhz f sub =32.768khz 2.0 - 4.0 v main operating frequency f main v dd =2~4v 0.4 - 4.2 mhz sub operating frequency f sub v dd =2~4v - 32.768 - khz operating temperature t opr -20 - 70 c
gms81c5108 12 june 2001 ver 1.0 7.3 dc electrical characteristics (ta=-20~70 c, v dd =av dd =2~4v, v ss =av ss =0v) parameter symbol condition specifications unit min. typ. max. input high voltage v ih1 r0~r3 0.7v dd - v dd v v ih2 reset , x in , int0~int2, ec0, si, sck 0.8v dd - v dd v ih3 sx in 0.8vreg - vreg input low voltage v il1 r0~r3 0 - 0.3 v dd v v il2 reset , x in , int0~int2, ec0, si, sck 0- 0.2v dd v il3 sx in 0-0.2vreg output high voltage v oh1 r0~r3, i oh1 =-0.7ma v dd -0.3 -- v v oh2 x out , i oh2 =-50 m av dd -0.5 -- v oh3 sx out , i oh3 =-5 m a vreg-0.3 - - output low voltage v ol1 r0~r3, wdtout , i ol1 =1ma - -0.4 v v ol2 x out , i ol2 =50 m a - -0.5 v ol3 sx out , i ol3 =5 m a - -0.5 input high leakage current i ih r0~r3, v in =v dd --1 m a input low leakage current i il r0~r3, v in =0v ---1 output high leakage current i oh remout, v dd =3v, v oh = v dd -1.0v -30 - -5 ma output low leakage current i ol remout, v dd =3v, v ol = 1.0v 0.5 - 3 pull-up resister r p1 r0~r3, v dd =3v 50 100 200 k w r p2 reset , v dd =3v (gms81c5108 mask option) 30 60 120 feed back resister r f1 main osc feedback resister v dd =3v 0.5 - 1.5 m w r f2 sub osc feedback resister v dd =3v 5. - 15 rc oscillator frequency f rc r=30k w , v dd =3v 123mhz vreg voltage vreg vreg=0.2uf 2.0 2.2 2.4 v supply current i dd1 main active mode v dd =4v 10%, x in =4mhz, sx in =0 -2.74.0 ma i dd2 main sleep mode v dd =4v 10%, x in =4mhz, sx in =0 -0.471.2 i dd3 stop mode v dd =4v 10%, x in =0, sx in =0 -2.010 m a i dd4 sub active mode 1 v dd =3v 10%, x in =0, s xin = 32.768khz - 35(70) 80(150) i dd5 sub sleep mode v dd =4v 10%, x in =0, s xin = 32.768khz -6.015 1. i dd4 is tested by only nop operation. the value of ( ) is tested at otp.
gms81c5108 june 2001 ver 1.0 13 7.4 lcd characteristics (ta=-20~70 c, v dd =av dd =2~4v, v ss =av ss =0v) 7.5 a/d converter characteristics (ta=25 c, v dd =3v, av dd =3.072v, v ss =av ss =0v) parameter symbol condition specifications unit min. typ. max. vlcdc output voltage vlcdc v dd =3v, ta=25 c, r1=1m w, r2 = 300k w 0.7 0.9 1.1 v lcd reference output voltage vcl0 external variable resistance (0 to 1m w) 0.9 - 2.0 double output voltage vcl1 c1~c4=0.47uf 1.9vcl0 2.0vcl0 - v triple output voltage vcl2 c1~c4=0.47uf 2.85vcl0 3.0vcl0 - lcd common output current i com output voltage deviation=0.2v 30 - - m a lcd segment output current i seg output voltage deviation=0.2v 5 - - parameter symbol condition specifications unit min. typ. max. analog power supply input voltage range av dd - av ss - av dd v analog input voltage range v an - av ss -0.3 - av dd +0.3 current following between av dd and av ss iav dd ---200 m a overall accuracy cain - - 1.0 2.0 lsb non linearity error nnle - - 1.0 2.0 differential non linearity error ndnle - - 1.0 2.0 zero offset error nzoe - - 0.5 1.5 full scale error nfse - - 0.25 0.5 gain error nge - - 1.0 1.5 conversion time tconv f main =4mhz --30 m s
gms81c5108 14 june 2001 ver 1.0 7.6 ac characteristics (ta=25 c, v dd =4v, av dd =4v, v ss =av ss =0v) figure 7-1 ac timing chart parameter symbol pins specifications unit min. typ. max. main operating frequency f mcp x in 0.455 - 4.19 mhz sub operating frequency f scp sx in 30 32.768 35 khz system clock frequency 1 t sys - 0.477 - 4.395 m s main oscillation stabilization time (4mhz) t mst x in , x out --20 ms main oscillation stabilization time (910khz) --60 main oscillation stabilization time (455khz) --100 sub oscillation stabilization time t sst sx in , sx out -12s external clock h or l pulse width t mcpw x in 80 - - ns t scpw sx in 5- - m s interrupt pulse width t iw int0, int1, int2 2 - - t sys reset input pulse l width t rst reset 8- - t sys event counter input h or l pulse width t ecw ec0 2 - - t sys 1.scmr=xxxx000x that is f main /2 x in 0.2v dd 0.8v dd 0.2v dd reset 0.2v dd 0.8v dd ec0 t rst t ecw t ecw 1/f mcp t mcpw t mcpw sx in 0.2v dd 0.8v dd 1/f scp t scpw t scpw t sys
gms81c5108 june 2001 ver 1.0 15 7.7 serial i/o characteristics (ta=25 c, v dd =av dd =2~4v, v ss =av ss =0v) figure 7-2 serial i/o timing chart parameter symbol pins specifications unit min. typ. max. sck input clock pulse period t scyc sck 2t sys +200 -- ns sck input clock h or l pulse width t sckw t sys +70 -- sck output clock cycle time t scyc 4t sys - 16t sys sck output clock h or l pulse width t sckw 2t sys -30 -- sck output clock delay time t ds - - 100 si input setup time (external sck) t esus si 100 - - si input setup time (internal sck) t isus 100 - - si input hold time t hs t sys +100 -- sck t sckw 0.2v dd t sckw t scyc 0.8v dd t ds t sus t hs 0.2v dd 0.8v dd 0.2v dd 0.8v dd so si
gms81c5108 16 june 2001 ver 1.0 7.8 typical characteristics these graphs and tables are for design guidance only and are not tested or guaranteed. in some graphs or tables, the datas presented are out- side specified operating range (e.g. outside specified v dd range). this is for information only and devices are guaranteed to operate properly only within the specified range. the data is a statistical summary of data collected on units from different lots over a period of time. typical repre- sents the mean of the distribution while max or min represents (mean + 3 s ) and (mean - 3 s ) respectively where s is standard deviation i ol - v ol , v dd =4.2v (ma) i ol 1.0 3.0 2.0 v ol (v) i oh - v oh , v dd =4.2v -8 -6 -4 -2 0 (ma) i oh 1.0 2.0 v oh (v) 70 c r0,r1,r2,r3 pin r - - - - ta 200 100 0 (k w ) -25 0 25 75 ta ( c) r v dd =4.0v r - - - - ta 100 50 0 (k w ) -25 0 25 75 ta ( c) reset pin r f main =4mhz v dd - v ih1 4 3 2 1 0 (v) v ih1 22.5 33.5 4 v dd (v) ta=25 c r0~r3 pin 40 30 10 -10 -12 -14 3.0 20 f main =4mhz v dd - v ih2 4 3 2 1 0 (v) v ih2 22.5 33.5 4 v dd (v) ta=25 c reset ,x in ,int0~int2,ec0.si.sck -16 4.0 25 c -20 c 4.0 -20 c 70 c 25 c 50 50 v dd =4.0v f main =4mhz v dd - v il2 2 1 0 (v) v il1 22.5 33.5 4 v dd (v) ta=25 c reset ,x in ,int0~int2,ec0.si.sck f main =4mhz v dd - v il1 2 1 0 (v) v il1 22.5 33.5 4 v dd (v) ta=25 c r0~r3 pin
gms81c5108 june 2001 ver 1.0 17 i sleep ( i dd5 ) - v dd 8 6 4 2 0 ( m a) i dd 22.533.54 v dd (v) sleep mode (sub opr.) ta= -20~70 c (main-clock) ta=25 c f main - v dd 4 3 2 1 0 (mhz) f main 2 2.5 3 3.5 4 v dd (v) ta=25 c r = 47k w i dd1 - v dd 4 3 2 1 0 (ma) i dd 22.533.54 v dd (v) normal mode (main opr.) 6 4 2 1 0 (mhz) f main 22.533.5 4.5 v dd (v) operating area i stop ( i dd3 ) - v dd 4 3 2 1 0 ( m a) i dd 22.5 33.5 4 v dd (v) stop mode i dd4 - v dd 100 75 50 25 0 ( m a) i dd 22.533.54 v dd (v) normal mode (sub opr.) i sleep ( i dd2 ) - v dd 400 300 200 100 0 ( m a) i dd 22.5 33.5 4 v dd (v) sleep mode (main opr.) f main =4mhz f sxin =32khz ta=25 c ta=25 c f main =0hz r = 68k w f sxin =32khz ta=25 c ta=25 c f main =4mhz 5 3 4 r = 100k w r = 20k w
gms81c5108 18 june 2001 ver 1.0 8. memory organization the gms81c5108 has separate address spaces for pro- gram memory, data memory and display memory. pro- gram memory can only be read, not written to. it can be up to 8k bytes of program memory. data memory can be read and written to up to 192 bytes including the stack area. dis- play memory has prepared 37 bytes for lcd. 8.1 registers this device has six registers that are the program counter (pc), a accumulator (a), two index registers (x, y), the stack pointer (sp), and the program status word (psw). the program counter consists of 16-bit register. figure 8-1 configuration of registers accumulator: the accumulator is the 8-bit general pur- pose register, used for data operation such as transfer, tem- porary saving, and conditional judgement, etc. the accumulator can be used as a 16-bit register with y register as shown below. figure 8-2 configuration of ya 16-bit register x, y registers: in the addressing mode which uses these index registers, the register contents are added to the spec- ified address, which becomes the actual address. these modes are extremely effective for referencing subroutine tables and memory tables. the index registers also have in- crement, decrement, comparison and data transfer func- tions, and they can be used as simple accumulators. stack pointer: the stack pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. stack pointer identifies the location in the stack to be accessed (save or restore). generally, sp is automatically updated when a subroutine call is executed or an interrupt is accepted. however, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. the stack can be located at any position within 00 h to bf h of the internal data memory. the sp is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initial- ization routine. normally, the initial value of bf h is used. program counter: the program counter is a 16-bit wide which consists of two 8-bit registers, pch and pcl. this counter indicates the address of the next instruction to be executed. in reset state, the program counter has reset rou- tine address (pc h :0ff h , pc l :0fe h ). program status word: the program status word (psw) contains several bits that reflect the current state of the cpu. the psw is described in figure 8-3. it contains the negative flag, the overflow flag, the break flag the half carry (for bcd operation), the interrupt enable flag, the zero flag, and the carry flag. [carry flag c] this flag stores any carry or borrow from the alu of cpu after an arithmetic operation and is also changed by the shift instruction or rotate instruction. a accumulator x register y register stack pointer program counter program status word x y sp pcl pch psw two 8-bit registers can be used as a ya 16-bit register y a y a caution: the stack pointer must be initialized by software be- cause its value is undefined after reset. example: to initialize the sp ldx #0bfh txsp ; sp ? bf h sp 0 stack address (00 h ~ bf h ) 15 0 87 hardware fixed
gms81c5108 june 2001 ver 1.0 19 [zero flag z] this flag is set when the result of an arithmetic operation or data transfer is 0 and is cleared by any other result. figure 8-3 psw (program status word) register [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software brk instruction. all inter- rupts are disabled when cleared to 0. this flag immedi- ately becomes 0 when an interrupt is served. it is set by the ei instruction and cleared by the di instruction. [half carry flag h] after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. this bit can not be set or cleared except clrv instruction with overflow flag (v). [break flag b] this flag is set by software brk instruction to distinguish brk from tcall instruction with the same vector ad- dress. [direct page flag g] this flag assigns ram page for direct addressing mode. in the direct addressing mode, addressing area is from zero page 00 h to 0ff h when this flag is "0". if it is set to "1", addressing area is assigned by rpr register (address 0f3 h ). it is set by setg instruction and cleared by clrg. [overflow flag v] this flag is set to 1 when an overflow occurs as the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction ex- ceeds + 127 (7f h ) or - 128 (80 h ). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, bit 6 of memory is copied to this flag. [negative flag n] this flag is set to match the sign bit (bit 7) status of the re- sult of a data or arithmetic operation. when the bit in- struction is executed, bit 7 of memory is copied to this flag. n negative flag v g b h i z c msb lsb reset value : 00 h psw overflow flag brk flag carry flag receives zero flag interrupt enable flag carry out half carry flag receives carry out from bit 1 of addition operlands select direct page when g=1, page is addressed by rpr
gms81c5108 20 june 2001 ver 1.0 figure 8-4 stack operation at execution of a call/tcall/pcall pcl pch 00bf sp after execution sp before execution 00bd 00be 00bd 00bc 00bf push down at acceptance of interrupt pcl pch 00bf 00bc 00be 00bd 00bc 00bf push down psw at execution of ret instruction pcl pch 00bf 00bf 00be 00bd 00bc 00bd pop up at execution of reti instruction pcl pch 00bf 00bf 00be 00bd 00bc 00bc pop up psw 0000 h 00bf h stack depth at execution of push instruction a 00bf 00be 00be 00bd 00bc 00bf push down sp after execution sp before execution push a (x,y,psw) at execution of pop instruction a 00bf 00bf 00be 00bd 00bc 00be pop up pop a (x,y,psw)
gms81c5108 june 2001 ver 1.0 21 8.2 program memory a 16-bit program counter is capable of addressing up to 64k bytes, but this device has 8k bytes program memory space only physically implemented. accessing a location above ffff h will cause a wrap-around to 0000 h . figure 8-5 shows a map of program memory. after reset, the cpu begins execution from reset vector which is stored in address fffe h and ffff h as shown in figure 8-6. as shown in figure 8-5, each area is assigned a fixed loca- tion in program memory. program memory area contains the user program. figure 8-5 program memory map page call (pcall) area contains subroutine program to reduce program byte length by using 2 bytes pcall in- stead of 3 bytes call instruction. if it is frequently called, it is more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall address, where it commences the execution of the service routine. the table call service area spaces 2-byte for every tcall: 0ffc0 h for tcall15, 0ffc2 h for tcall14, etc., as shown in figure 8-7. example: usage of tcall the interrupt causes the cpu to jump to specific location, where it commences the execution of the service routine. the external interrupt 0, for example, is assigned to loca- tion 0fffa h . the interrupt service locations spaces 2-byte interval: 0fff8 h and 0fff9 h for external interrupt 1, 0fffa h and 0fffb h for external interrupt 0, etc. any area from 0ff00 h to 0ffff h , if it is not going to be used, its service location is available as general purpose program memory. figure 8-6 interrupt vector area program memory tcall area interrupt vector area e000 h feff h ff00 h ffc0 h ffdf h ffe0 h ffff h pcall area lda #5 tcall 0fh ; 1byte instruction :; instead of 2 bytes :; normal call ; ;table call routine ; func_a: lda lrg0 ret ; func_b: lda lrg1 ret ; ;table call add. area ; org 0ffc0h ; tcall address area dw func_a dw func_b 1 2 0ffe0 h e2 address vector area memory e4 e6 e8 ea ec ee f0 f2 f4 f6 f8 fa fc fe - - - - serial i/o interrupt vector area ad converter interrupt vector area remocon interrupt vector area timer/counter 1 interrupt vector area timer/counter 0 interrupt vector area external interrupt 1 vector area basic interval timer interrupt vector area key scan interrupt vector area reset vector area external interrupt 0 vector area external interrupt 2 vector area watch timer interrupt vector area - means reserved area. note:
gms81c5108 22 june 2001 ver 1.0 figure 8-7 pcall and tcall memory area pcall ? ? ? ? rel 4f35 pcall 35 h tcall ? ? ? ? n 4a tcall 4 0ffc0 h c1 address program memory c2 c3 c4 c5 c6 c7 c8 0ff00 h address pcall area memory 0ffff h pcall area (256 bytes) * means that the brk software interrupt is using same address with tcall0. note: tcall 15 tcall 14 tcall 13 tcall 12 tcall 11 tcall 10 tcall 9 tcall 8 tcall 7 tcall 6 tcall 5 tcall 4 tcall 3 tcall 2 tcall 1 tcall 0 / brk * c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df 4f ~ ~ ~ ~ next 35 0ff35 h 0ff00 h 0ffff h 11111111 11010110 01001010 pc: f h f h d h 6 h 4a ~ ~ ~ ~ 25 0ffd6 h 0ff00 h 0ffff h d1 next 0ffd7 h ? 0d125 h reverse
gms81c5108 june 2001 ver 1.0 23 example: the usage software example of vector address and the initialize part. org 0ffe0h dw not_used dw not_used dw not_used dw not_used dw wt_int ; watch timer dw sio ; serial i/o dw ad_con ; ad converter dw carrier_int ; carrier dw int2 ; int.2 dw tmr1_int ; timer-1 dw tmr0_int ; timer-0 dw int1 ; int.1 dw int0 ; int.0 dw bit_int ; bit dw key_int ; key scan dw reset ; reset org 0f000h ;******************************************** ; main program * ;******************************************** ; reset: di ;disable all interrupts clrg ldx #0 ram_clr: lda #0 ;ram clear(!0000 h ->!00bf h ) sta {x}+ cmpx #0c0h bne ram_clr ; ldx #0bfh ;stack pointer initialize txsp ; call lcd_clr ;clear lcd display memory ; ldm r0, #0 ;normal port 0 ldm r0dr,#1000_0010b ;normal port direction ldm r0pu,#1000_0010b ;pull up selection set ldm r0cr,#0000_0001b ;r0 port open drain control : : ldm scmr,#1111_0000b ;system clock control : :
gms81c5108 24 june 2001 ver 1.0 8.3 data memory figure 8-8 shows the internal data memory space availa- ble. data memory is divided into four groups, a user ram, control registers, stack, and lcd memory. figure 8-8 data memory map user memory the gms81c5108 has 192 8 bits for the user memory (ram). there are two page internal ram. page is selected by g- flag and ram page selection register rpr. when g-flag is cleared to 0, always page 0 is selected regardless of rpr value. if g-flag is set to 1, page will be selected ac- cording to rpr value. figure 8-9 ram page configuration control registers the control registers are used by the cpu and peripheral function blocks for controlling the desired operation of the device. therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and i/o ports. the control registers are in address range of 0c0 h to 0ff h . note that unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in gen- eral return random data, and write accesses will have an in- determinate effect. more detailed informations of each register are explained in each peripheral section. note: write only registers can not be accessed by bit ma- nipulation instruction. do not use read-modify-write instruc- tion. use byte manipulation instruction. example; to write at ckctlr ldm ckctlr,#05h ;divide ratio ? 8 stack area the stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. when returning from the processing routine, executing the subroutine return instruction [ret] restores the contents of the program counter from the stack; executing the interrupt return instruction [reti] restores the contents of the pro- gram counter and flags. the save/restore locations in the stack are determined by the stack pointed (sp). the sp is automatically decreased after the saving, and increased before the restoring. this means the value of the sp indicates the stack location number for the next save. refer to figure 8-4 on page 20. lcd display memory lcd display data area is handled in lcd section. see "19.3 lcd display memory" on page 73. user memory (including stack area) peripheral control registers memory 0000 h 00bf h 00c0 h 00ff h 0100 h 0124 h page0 page1 lcd display (192 bytes) page 0 page 0: 00~ff h page 1 page 1: 100~124 h rpr=1, g=1 rpr=0, g=0
gms81c5108 june 2001 ver 1.0 25 address register name symbol r/w initial value addressing mode page 76543210 00c0 r0 port data register r0 r/w 0 0 0 0 0 0 0 0 byte, bit 1 32 00c1 r1 port data register r1 r/w 0 0 0 0 0 0 0 0 byte, bit 32 00c2 r2 port data register r2 r/w - - - - 0 0 0 0 byte, bit 33 00c3 r3 port data register r3 r/w - - - - 0 0 0 0 byte, bit 33 00c8 r0 port i/o direction register r0dr w 0 0 0 0 0 0 0 0 byte 2 32 00c9 r1 port i/o direction register r1dr w 0 0 0 0 0 0 0 0 byte 32 00ca r2 port i/o direction register r2dr w - - - - 0 0 0 0 byte 33 00cb r3 port i/o direction register r3dr w - - - - 0 0 0 0 byte 33 00d0 r0 port pull-up register r0pu w 0 0 0 0 0 0 0 0 byte 32 00d1 r1 port pull-up register r1pu w 0 0 0 0 0 0 0 0 byte 32 00d2 r2 port pull-up register r2pu w - - - - 0 0 0 0 byte 33 00d3 r3 port pull-up register r3pu w - - - - 0 0 0 0 byte 33 00d4 r0 port open drain control register r0cr w 0 0 0 0 0 0 0 0 byte 32 00d5 r1 port open drain control register r1cr w 0 0 0 0 0 0 0 0 byte 32 00d6 r2 port open drain control register r2cr w - - - - 0 0 0 0 byte 33 00d7 r3 port open drain control register r3cr w - - - - 0 0 0 0 byte 33 00d8 ext. interrupt edge selection register iesr r/w - - 0 0 0 0 0 0 byte, bit 69 00d9 port selection register pmr r/w - 0 - 0 0 0 0 0 byte, bit 32 00da interrupt enable low register ienl r/w - 0 0 0 0 - - - byte, bit 65 00db interrupt enable high register ienh r/w - 0 0 0 0 0 0 0 byte, bit 65 00dc interrupt request flag low register irql r/w - 0 0 0 0 - - - byte, bit 65 00dd interrupt request flag high register irqh r/w - 0 0 0 0 0 0 0 byte, bit 65 00de sleep mode register smr r/w - - - - - - - 0 byte, bit 39 00e0 timer 0 mode register tm0 r/w - - 0 0 0 0 0 0 byte, bit 45 00e1 timer 0 counter register t0 r 0 0 0 0 0 0 0 0 byte, bit 45 timer 0 data register tdr0 w 11111111 byte 45 timer 0 input capture register cdr0 r 0 0 0 0 0 0 0 0 byte, bit 45 00e2 timer 1 mode register tm1 r/w 0 0 0 0 0 0 0 0 byte, bit 45 00e3 timer 1 data register tdr1 w 11111111 byte 45 pwm0 pulse period register t1ppr w 1 1 1 1 1 1 1 1 byte 45 00e4 timer 1 counter register t1 r 0 0 0 0 0 0 0 0 byte, bit 45 timer 1 input capture register cdr1 r 0 0 0 0 0 0 0 0 byte, bit 45 pwm0 pulse duty register t1pdr r/w 00000000 byte, bit 45 00e5 pwm0 high register pwmhr w - - - - 0 0 0 0 byte 45 00ec a/d converter mode register admr r/w - 0 - - 0 0 0 1 byte, bit 58 00ed a/d converter data register addr r x x x x x x x x byte, bit 58 table 8-1 control registers
gms81c5108 26 june 2001 ver 1.0 00ef watch timer mode register wtmr r/w - 0 0 0 0 0 0 0 byte, bit 56 00f0 key scan mode register ksmr r/w 0 0 0 0 0 0 0 0 byte, bit 70 00f1 lcd control register lcr r/w 0 0 0 0 0 0 0 0 byte, bit 72 00f3 ram paging register rpr r/w - - - - - - 0 0 byte, bit 73 00f4 basic interval timer register bitr r 0 0 0 0 0 0 0 0 byte, bit 43 clock control register ckctlr w - - - - 0 1 1 1 byte 43 00f5 system clock mode register scmr r/w 0 0 0 0 0 0 0 0 byte, bit 34 00f6 remocon mode register rmr r/w - 0 0 0 0 0 0 0 byte, bit 76 00f7 carrier frequency high selection cfhs w - - 1 1 1 1 1 1 byte 76 00f8 carrier frequency low selection cfls w - - 1 1 1 1 1 1 byte 76 00f9 remocon data high register rdhr w 1 1 1 1 1 1 1 1 byte 76 00fa remocon data low register rdlr w 1 1 1 1 1 1 1 1 byte 76 remocon data counter rdc r 0 0 0 0 0 0 0 0 byte, bit 76 00fb remocon output data register rodr r/w - - - - - - - 0 byte, bit 76 00fc remocon output buffer rob r/w - - - - - - - 0 byte, bit 76 00fd buzzer data register bdr w 0 0 0 0 0 0 0 0 byte 60 00fe serial i/o mode register siom r/w 0 0 0 0 0 0 0 1 byte, bit 62 00ff serial i/o data register siod r/w x x x x x x x x byte, bit 62 1. byte, bit means that register can be addressed by not only bit but byte manipulation instruction. 2. byte means that register can be addressed by only byte manipulation instruction. on the other hand, do not use any read-mod ify-write instruction such as bit manipulation. address register name symbol r/w initial value addressing mode page 76543210 table 8-1 control registers
gms81c5108 june 2001 ver 1.0 27 8.4 addressing mode the gms81c5108 uses six addressing modes; ? register addressing ? immediate addressing ? direct page addressing ? absolute addressing ? indexed addressing ? register-indirect addressing (1) register addressing register addressing accesses the a, x, y, c and psw. (2) immediate addressing ? ? ? ? #imm in this mode, second byte (operand) is accessed as a data immediately. example: 0435 adc #35 h when g-flag is 1, then ram address is defined by 16-bit address which is composed of 8-bit ram paging register (rpr) and 8-bit immediate data. example: g=1, rpr=01 h e45535 ldm 35 h ,#55 h (3) direct page addressing ? ? ? ? dp in this mode, a address is specified within direct page. example; g=0 c535 lda 35 h ;a ? ram[35 h ] (4) absolute addressing ? ? ? ? !abs absolute addressing sets corresponding memory data to data, i.e. second byte (operand i) of command becomes lower level address and third byte (operand ii) becomes upper level address. with 3 bytes command, it is possible to access to whole memory area. adc, and, cmp, cmpx, cmpy, eor, lda, ldx, ldy, or, sbc, sta, stx, sty example; 0735f0 adc !0f035 h ;a ? rom[0f035 h ] 35 a+35 h +c ? a 04 memory e4 0f100 h data ? 55 h ~ ~ ~ ~ data 0135 h 35 0f102 h 55 0f101 h ? data 35 35 h 0e551 h data ? a ? ~ ~ ~ ~ c5 0e550 h 07 0f100 h ~ ~ ~ ~ data 0f035 h f0 0f102 h 35 0f101 h ? a+data+c ? a address: 0f035
gms81c5108 28 june 2001 ver 1.0 the operation within data memory (ram) asl, bit, dec, inc, lsr, rol, ror example; addressing accesses the address 0135 h regard- less of g-flag and rpr. 981501 inc !0115 h ;a ? rom[115 h ] (5) indexed addressing x indexed direct page (no offset) ? ? ? ? {x} in this mode, a address is specified by the x register. adc, and, cmp, eor, lda, or, sbc, sta, xma example; x=15 h , g=1, rpr=01 h d4 lda {x} ;acc ? ram[x]. x indexed direct page, auto increment ? ? ? ? {x}+ in this mode, a address is specified within direct page by the x register and the content of x is increased by 1. lda, sta example; g=0, x=35 h db lda {x}+ x indexed direct page (8 bit offset) ? ? ? ? dp+x this address value is the second byte (operand) of com- mand plus the data of -register. and it assigns the mem- ory in direct page. adc, and, cmp, eor, lda, ldy, or, sbc, sta sty, xma, asl, dec, inc, lsr, rol, ror example; g=0, x=0f5 h c645 lda 45 h +x 98 0f100 h ~ ~ ~ ~ data 115 h 01 0f102 h 15 0f101 h ? data+1 ? data address: 0115 data d4 115 h 0e550 h data ? a ? ~ ~ ~ ~ data db 35 h data ? a ? ~ ~ ~ ~ 36h ? x data 45 3a h 0e551 h data ? a ? ~ ~ ~ ~ c6 0e550 h 45 h +0f5 h =13a h
gms81c5108 june 2001 ver 1.0 29 y indexed direct page (8 bit offset) ? ? ? ? dp+y this address value is the second byte (operand) of com- mand plus the data of y-register, which assigns memory in direct page. this is same with above (2). use y register instead of x. y indexed absolute ? ? ? ? !abs+y sets the value of 16-bit absolute address plus y-register data as memory. this addressing mode can specify mem- ory in whole area. example; y=55 h d500fa lda !0fa00 h +y (6) indirect addressing direct page indirect ? ? ? ? [dp] assigns data address to use for accomplishing command which sets memory data (or pair memory) by operand. also index can be used with index register x,y. jmp, call example; g=0 3f35 jmp [35 h ] x indexed indirect ? ? ? ? [dp+x] processes memory data as data, assigned by 16-bit pair memory which is determined by pair data [dp+x+1][dp+x] operand plus x-register data in direct page. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, x=10 h 1625 adc [25 h +x] d5 0f100 h data ? a ~ ~ ~ ~ data 0fa55 h 0fa00 h +55 h =0fa55 h fa 0f102 h 00 0f101 h ? 0a 35 h jump to address 0e30a h ~ ~ ~ ~ 35 0fa00 h e3 36 h ? 3f 0e30a h next ~ ~ ~ ~ 05 35 h 0e005 h ~ ~ ~ ~ 25 0fa00 h e0 36 h 16 0e005 h data ~ ~ ~ ~ a + data + c ? a 25 + x(10) = 35 h ?
gms81c5108 30 june 2001 ver 1.0 y indexed indirect ? ? ? ? [dp]+y processes memory data as data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by operand in di- rect page plus y-register data. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, y=10 h 1725 adc [25 h ]+y absolute indirect ? ? ? ? [!abs] the program jumps to address specified by 16-bit absolute address. jmp example; g=0 1f25e0 jmp [!0e025 h ] 05 25 h 0e005 h + y(10) = 0e015 h ~ ~ ~ ~ 25 0fa00 h e0 26 h ? 17 0e015 h data ~ ~ ~ ~ a + data + c ? a 25 0e025 h jump to ~ ~ ~ ~ e0 0fa00 h e7 0e026 h ? 25 0e725 h next ~ ~ ~ ~ 1f program memory address 0e725 h
gms81c5108 june 2001 ver 1.0 31 9. i/o ports the gms81c5108 has seven ports (r0, r1, r2 and r3), and lcd segment port (seg0~seg36), and lcd com- mon port (com0~com3). these ports pins may be multiplexed with an alternate function for the peripheral features on the device. 9.1 registers for port port data registers the port data registers (r0, r1, r2, r3) are represented as a d-type flip-flop, which will clock in a value from the internal bus in response to a write to data register signal from the cpu. the q output of the flip-flop is placed on the internal bus in response to a read data register signal from the cpu. the level of the port pin itself is placed on the internal bus in response to read data register signal from the cpu. some instructions that read a port activating the read register signal, and others activating the read pin signal. port direction registers all pins have data direction registers which can define these ports as output or input. a 1 in the port direction register configure the corresponding port pin as output. conversely, write 0 to the corresponding bit to specify it as input pin. for example, to use the even numbered bit of r0 as output ports and the odd numbered bits as input ports, write 55 h to address 0c8 h (r0 port direction reg- ister) during initial setting as shown in figure 9-1. all the port direction registers in the gms81c5108 have 0 written to them by reset function. on the other hand, its in- itial status is input. figure 9-1 example of port i/o assignment pull-up control registers the r0, r1,r2 and r3 ports have internal pull-up resis- tors. figure 9-2 shows a functional diagram of a typical pull-up port. it is connected or disconnected by pull-up control register (r n pu). the value of that resistor is typi- cally 100k w . refer to dc characteristics for more details. when a port is used as key input, input logic is firmly ei- ther low or high, therefore external pull-down or pull-up resisters are required practically. the gms81c5108 has internal pull-up, it can be logic high by pull-up that can be able to configure either connect or disconnect individually by pull-up control registers r n pu. when ports are configured as inputs and pull-up resistor is selected by software, they are pulled to high. figure 9-2 pull-up port structure open drain port registers the r0, r1, r2 and r3 ports have open drain port resistors r0cr~r3cr. figure 9-3 shows an open drain port configuration by control reg- ister. it is selected as either push-pull port or open-drain port by r0cr, r1cr, r2cr and r3cr. figure 9-3 open-drain port structure i : input port write 55 h to port r0 direction register 0 1 0 1 0 1 0 1 i o i o i o i o r0 data r0 direction r1 data r1 direction 0c0 h 0c1 h 0c8 h 0c9 h 76543210 bit 76543210 port o : output port ~ ~ ~ ~ pull-up resistor port pin 1: connect 0: disconnect pull-up control bit vdd gnd vdd port pin 1: open drain 0: push-pull open drain port selection bit gnd
gms81c5108 32 june 2001 ver 1.0 9.2 i/o ports configuration r0 ports r0 is an 8-bit cmos bidirectional i/o port (address 0c0 h ). each i/o pin can independently used as an input or an output through the r0dr register (address 0c8 h ). r0 has internal pull-ups that is independently connected or disconnected by r0pu. the control registers for r0 are shown below. in addition, port r0 and r3 are multiplexed with various special features. the control register pmr (address 0d9h) controls the selection of alternate function. after reset, this value is 0, port may be used as normal i/o port. to use alternate function such as external interrupt rather than normal i/o, write 1 in the corresponding bit of pmr0. . r1 ports r1 is an 8-bit cmos bidirectional i/o port (address 0c1 h ). each i/o pin can independently used as an input or an output through the r1dr register (address 0c9 h ). r1 has internal pull-ups that is independently connected or disconnected by register r1pu. if the key scan function is used, these pin can input the key switch signal without ex- ternal pull-up registers. for more details refer to "18. key scan" on page 70. the control registers for r1 are shown below. pwmo (pwm output) 0: r31 port 1: pwm r0 data register r0 address : 0c0 h reset value : 00 h r07 r06 r05 r04 r03 r02 r01 r00 port direction r0 direction register r0dr address : 0c8 h reset value : 00 h 0: input 1: output pull-up select r0 pull-up r0pu address :0d0 h reset value : 00 h 0: without pull-up 1: with pull-up open drain select r0 open drain r0cr address :0d4 h reset value : 00 h 0: no open drain 1: open drain port mode register pmr address :0d9 h reset value : -0-00000 b - pwmo - buz ec0 int2 int1 int0 buz (buzzer output) 0: r04 port 1: buz ec0 (timer0 event input) 0: r03 port 1: ec0 int2 (external interrupt) 0: r02 port 1: int2 int1 (external interrupt) 0: r01 port 1: int1 int0 (external interrupt) 0: r00 port 1: int0 selection register selection register port pin alternate function r00 r01 r02 r03 r04 r31 int0 (external interrupt 0) int1 (external interrupt 1) int2 (external interrupt 2) ec0 (timer0 event input) buz (buzzer output) pwm (pwm output) r1 data register r1 address : 0c1 h reset value : 00 h port direction r1 direction register r1dr address : 0c9 h reset value : 00 h 0: input 1: output pull-up select r1 pull-up r1pu address : 0d1 h reset value : 00 h 0: without pull-up 1: with pull-up r17 r16 r15 r14 r13 r12 r11 r10 open drain select r1 open drain r1cr address :0d5 h reset value : 00 h 0: no open drain 1: open drain key input select key scan mode register ksmr address :0f0 h reset value : 00 h 0: port selection 1: ks selection selection register selection register
gms81c5108 june 2001 ver 1.0 33 port r1 is multiplexed with various special features.the control registers controls the selection of alternate func- tion. after reset, this value is 0, port may be used as nor- mal i/o port. the way to select alternate function such as comparator input or buzzer will be shown in each periph- eral section. in addition, r1 port is used as key scan function which op- erate with normal input port. input or output is configured automatically by each func- tion register (ksmr) regardless of r1dr. r2 port r2 is a 4-bit cmos bidirectional i/o port (address 0c2 h ). each i/o pin can independently used as an input or an out- put through the r2dr register (address 0ca h ). r2 has internal pull-ups that is independently connected or disconnected by r2pu (address 0d2 h ). the control regis- ters for r2 are shown as below. r3 port r3 is a 4-bit cmos bidirectional i/o port (address 0c3 h ). each i/o pin can independently used as an input or an out- put through the r3dr register (address 0cb h ). seg0~seg36 segment signal output pins for the lcd display. see "19. lcd driver" on page 71 for details. com0~com3 common signal output pins for the lcd display. see "19. lcd driver" on page 71 for details. seg34~seg36 and com1~com3 are selected by lcdd of the lcr register. r2 data register r2 address: 0c2 h reset value: ----0000 b port direction r2 direction register r2dr address : 0ca h reset value : ----0000 b 0: input 1: output pull-up select r2 pull-up r2pu address : 0d2 h reset value : ----0000 b 0: without pull-up 1: with pull-up r23 r22 r21 r20 - - - - - - - - - - - - pull-up select r2 open drain r2cr address : 0d6 h reset value : ----0000 b 0: no open drain 1: open drain - - - - selection register selection register r3 data register r3 address: 0c3 h reset value: ----0000 b port direction r3 direction register r3dr address : 0cb h reset value : ----0000 b 0: input 1: output pull-up select r3 pull-up r3pu address : 0d3 h reset value : ----0000 b 0: without pull-up 1: with pull-up r33 r32 r31 r30 - - - - - - - - - - - - pull-up select r3 open drain r3cr address : 0d7 h reset value : ----0000 b 0: no open drain 1: open drain - - - - selection register selection register
gms81c5108 34 june 2001 ver 1.0 10. clock generator as shown in figure 10-1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the cpu and the peripheral hardware. it con- tains two oscillators: a main-frequency clock oscillator and a sub-frequency clock oscillator. power consumption can be reduced by switching them to the low power operation frequency clock can be easily obtained by attaching a res- onator between the x in and x out pin and the sx in and sx out pin, respectively. the system clock can also be ob- tained from the external oscillator. the clock generator produces the system clocks forming clock pulse, which are supplied to the cpu and the periph- eral hardware. the internal system clock can be selected by bit2, and bit3 of the system clock mode register (sc- mr). the registers are shown in figure 10-2. to the peripheral block, the clock among the not-divided original clocks, divided by 2 , 4,..., up to 1024 can be pro- vided. peripheral clock is enabled or disabled by stop in- struction. the peripheral clock is controlled by clock control register (ckctlr). see "11. basic interval timer" on page 43 for details. figure 10-1 block diagram of clock generator cpu clock instruction cycle time f main = 4mhz f sub = 32.768khz ? 2 0.5 us 61 us ? 8 2.0 us 244 us ? 16 4.0 us 488 us ? 64 16.0 us 1953 us internal system clock sx in prescaler 0 1 x in ? 1 peripheral clock mux ? 2 ? 4 ? 8 ? 16 ? 128 ? 256 ? 512 ? 1024 ? 32 ? 64 ? 2 ? 8 ? 16 ? 64 select clock scs[1:0] osc stop sycc<1> sycc<0> stop mode sleep mode ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ** clock is frozen by stop or sleep[smr.0] instruction. ** clock is released 1) by bit overflow when previos state has been stop mode. 2) by interrupts when previos state has been sleep mode. prescaler f ex (hz) ps0 ps3 ps2 ps4 ps1 ps10 ps9 ps5 ps6 ps7 4m frequency period 4m 1m 500k 250k 2m 125k 62.5k 250n 500n 1u 2u 4u 8u 16u 32u 64u 256u 128u 3.906k 7.183k 15.63k 31.25k ps8
gms81c5108 june 2001 ver 1.0 35 the system clock is decided by bit1 of the system clock mode register, scmr. in selection sub clock, to oscillate or stop the main clock is decided by bit0 of scmr. on the initial reset, internal system clock is ps1 which is the fastest and other clock can be provided by bit2 and bit3 of scmr. figure 10-2 scmr : system clock control registers r/w r/w r/w r/w sycc[1:0] (system clock control) 00: main clock on 01: main clock on 10: sub clock on (main clock on) 11: sub clock on (main clock off) scs[1:0] (system clock source select) 00: f main ? 2 01: f main ? 8 initial value: 00 h address: 0f5 h scmr (system clock mode register) 10: f main ? 16 11: f main ? 64 msb lsb or f sub ? 2 or f sub ? 8 or f sub ? 16 or f sub ? 64 r/w r/w r/w r svd[1:0] (svd flag) svd0 : set at vdd=2.2v svd1 : set at vdd=1.7v svrt (system reset control by svd1 bit) 0 : system reset by svd1 flag 1 : dont system reset by svd1 flag (freeze) sven (svd operation enable bit) 0 : svd operation enable 1 : svd operation disable * the values of 1.7v and 2.2v could be changed by 0.2v according to the process of work.
gms81c5108 36 june 2001 ver 1.0 10.1 operation mode the system clock controller starts or stops the main-fre- quency clock oscillator and switches between the sub fre- quency clock. the operating mode is generally divided into the main active mode and the sub active mode, which are controlled by system clock mode register (scmr). figure 10-3 shows the operating mode transition diagram. system clock control is performed by the system clock mode register, scmr. during reset, this register is initial- ized to 0 so that the main-clock operating mode is select- ed. main active mode this mode is fast-frequency operating mode. the cpu and the peripheral hardwares are operated on the high-frequency clock. at reset release, this mode is in- voked. sub active mode this mode is low-frequency operating mode in this mode, the cpu and the peripheral hardware clock are provided by low-frequency clock oscillation, so power consumption can be reduced. sleep mode in this mode, the cpu clock stops while peripherals and the oscillation source continue to operate normally. stop mode in this mode, the system operations are all stopped, holding the internal states valid immediately before the stop at the low power consumption level. figure 10-3 operating mode main active mode main : stop or oscillation (case of **1) sub : oscillation main : oscillation sub : oscillation sub active mode 1 sub active mode 2 stop / sleep mode * note1 / * note2 system clock : main main : oscillation sub : oscillation system clock : sub set1 scmr.1 clr1 scmr.1 * n ote 3 * no t e1 / n ote 2 st o p / ( ** 1 ) s e t 1 s mr .0 ldm scmr,#03h stop / set1 smr.0 clr1 scmr.0 set1 scmr.0 * note1 / * note2 stop / set1 smr.0 system clock : stop main : stop sub : oscillation system clock : sub * note1 : stop released by reset, key scan watch timer interrupt timer interrupt (event counter) sio (external clock) external interrupt * note2 : sleep released by reset, key scan all interrupts * note3 : this is sequential 1) clr1 scmr.0 2) oscillation stabilation time (more than 65ms) 3) clr1 scmr.1 - sub clock cannot be stopped by stop instruction.
gms81c5108 june 2001 ver 1.0 37 10.2 operation mode switching in the main active mode, only the high-frequency clock os- cillator is used. in the sub active mode, the low-frequency clock oscilla- tion is used, so the low power voltage operation or the low power consumption operation can be enabled. instruction execution does not stop during the change of operation mode. in this case, some peripheral hardware capabilities may be affected. for details, refer to the description of the relevant operation. the following describes the switching between the main active mode and the sub active mode. during reset, the system clock mode register is initialized at the main active mode. it must be set to the sub active mode for reducing the power consumption. switching from main active to sub active first, write 02 h into lower 2 bits of scmr to switch the main system clock to the sub-frequency clock. next, write 03 h to turn off main frequency oscillation. example: : : : ldm scmr,#02 h ;switch to sub active ldm scmr,#03 h ;turn off main clock : : returning from sub active to main active first, write 02 h into lower 2 bits of the scmr to turn on the main-frequency oscillation. this time, the stabilization (warm-up) time needs to be taken by the software delay routine. sub active mode can also be released by setting the reset pin to low, which immediately performs the reset operation. after reset, the gms81c5108 is placed in main active mode. example: : : : ldm scmr,#02 h ;turn on main-clock call delay ;wait until stable ldm scmr,#0 ;move to main active : : : ;about 65ms software delay delay: lda #0 delay0: inc a cmp #85h bcc delay0 ret shifting from the normal operation to the sleep mode by setting bit 0 of smr, the cpu clock stops and the sleep mode is invoked. the cpu stops while other pe- ripherals are operate normally. the way of release from this mode is reset and all avail- able interrupts. for more detail, see " sleep mode" on page 39 shifting from the normal operation to the stop mode by executing stop instruction, the main-frequency clock oscillation stops and the stop mode is invoked. but sub- frequency clock oscillation is operated continuously. after the stop operation is released by reset, the opera- tion mode is changed to main active mode. the methods of release are reset, key scan interrupt, watch timer interrupt, timer/event counter1 (ec0 pin), sio (external clock) and external interrupt. for more details, see " stop mode" on page 40. note: in the stop and slow operating modes, the power consumption by the oscillator and the internal hardware is reduced. however, the power for the pin interface (depend- ing on external circuitry and program) is not directly associ- ated with the low-power consumption operation. this must be considered in system design as well as interface circuit design.
gms81c5108 38 june 2001 ver 1.0 figure 10-4 system clock switching timing operation clock ~ ~ ~ ~ sub-clock operation main-clock operation sub freq. clock main freq. clock (x in pin) (sx in pin) changed to the sub-clock scmr ? xxxx xx10 b ~ ~ ~ ~ ~ ~ operation clock ~ ~ main-clock operation stabilizing time > 60ms sub freq. clock main freq. clock (x in pin) (sx in pin) changed to the transition changed to the main-clock scmr ? xxxx xx10 b scmr ? xxxx xx00 b ~ ~ ~ ~ sub-clock operation ~ ~ (a) main active mode ? ? ? ? sub active mode (b) sub active mode ? ? ? ? main active mode or xxxx xx01 b turn off main clock scmr ? xxxx xx11 b
gms81c5108 june 2001 ver 1.0 39 10.3 power saving operation gms81c5108 has 2 power-saving mode. in power-saving mode, power consumption is reduced considerably that in battery operation battery life can be extended a lot. sleep mode is entered by setting bit 0 of sleep mode reg- ister (smr), and stop mode is entered by stop instruc- tion. sleep mode in this mode, the internal oscillation circuits remain active. oscillation continues and peripherals are operate normally but cpu stops. movement of all peripherals is shown in table 10-1. sleep mode is entered by setting bit 0 of smr (address 0de h ). it is released by reset or interrupt. to be released by in- terrupt, interrupt should be enabled before sleep mode. figure 10-5 sleep mode register figure 10-6 sleep mode release timing by external interrupt . figure 10-7 sleep mode release timing by reset pin sleep mode register smr address : 0de h reset value : -------0 b 0: release sleep mode 1: enter sleep mode ------- oscillator normal operation stand-by mode normal operation interrupt internal cpu clock release set bit 0 of smr (x in or sx in pin) ~ ~ ~ ~ oscillator (x in or sx in pin) 0 bit counter 1 fe ff 0 12 ~ ~ t st = 62.5ms ~ ~ ~ ~ reset internal cpu clock clear & start ~ ~ ~ ~ normal operation stand-by mode normal operation release set bit 0 of smr ~ ~ ~ ~ ~ ~ at 4.19mhz by hardware ~ ~ 2 t st = x 256 f main ? 1024 1
gms81c5108 40 june 2001 ver 1.0 stop mode for applications where power consumption is a critical factor, device provides stop mode for reducing power consumption. start the stop operation the stop mode can be entered by stop instruction dur- ing program execution. in stop mode, the on-chip main- frequency oscillator, system clock, and peripheral clock are stopped (watch timer clock is oscillating continuous- ly:. with the clock frozen, all functions are stopped, but the on-chip ram and control registers are held. the port pins output the values held by their respective port data register, the port direction registers. the status of peripherals during stop mode is shown below. table 10-2 clock operation of stop and sleep mode note: since the x in pin is connected internally to gnd to avoid current leakage due to the crystal oscillator in stop mode, do not use stop instruction when an external clock is used as the main system clock. in the stop mode of operation, v dd can be reduced to min- imize power consumption. be careful, however, that v dd is not reduced before the stop mode is invoked, and that v dd is restored to its normal operating level before the stop mode is terminated. the reset should not be activated before v dd is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. and after stop instruction, at least two or more nop in- struction should be written as shown in example below. peripheral stop mode sleep mode cpu all cpu operations are disabled all cpu operations are disabled ram retain retain lcd driver operates continuously operates continuously basic interval timer halted operates continuously timer/event counter 0,1 halted (only when the event counter mode is enabled, timer 0,1 operates normally) timer/event counter 0,1 operates continuously watch timer operates continuously operates continuously key scan active active main-oscillation stop (x in =l, x out =l) oscillation 1 sub-oscillation oscillation oscillation i/o ports retain retain control registers retain retain release method by reset, key scan interrupt, sio interrupt, watch timer interrupt, timer interrupt (ec0), and external interrupt by reset, all interrupts table 10-1 peripheral operation during power saving mode 1. refer to the table 10-2 operating clock source main operating mode main sleep mode sub operating mode sub sleep mode stop mode main clock oscillation oscillation scmr<1:0> 00,01,10 ? oscillation 11 ? stop scmr<1:0> 00,01,10 ? oscillation 11 ? stop stop sub clock oscillation oscillation oscillation oscillation oscillation system clock active stop active stop stop peri. clock active active active active stop
gms81c5108 june 2001 ver 1.0 41 example) : ldm ckctlr,#0000_1111b stop nop nop : the interval timer register ckctlr should be initial- ized by software in order that oscillation stabilization time should be longer than 20ms before stop mode. release the stop mode the exit from stop mode is using hardware reset or exter- nal interrupt, watch timer, sio interrupt, key scan or timer interrupt (ec0). to release stop mode, corresponding interrupt should be enabled before stop mode. specially as a clock source of timer/event counter, ec0 pin can release it by timer/event counter interrupt re- quest reset redefines all the control registers but does not change the on-chip ram. external interrupts allow both on-chip ram and control registers to retain their values. start-up is performed to acquire the time for stabilizing os- cillation. during the start-up, the internal operations are all stopped. figure 10-8 stop mode release timing by external interrupt figure 10-9 stop mode release timing by reset before executing stop instruction, basic interval timer must be set oscillator (x in pin) ~ ~ n 0 bit counter n+1 n+2 n+3 ~ ~ normal operation stop operation normal operation 1 fe ff 0 12 ~ ~ ~ ~ ~ ~ t st > 20ms ~ ~ ~ ~ external interrupt internal clock clear stop instruction executed ~ ~ ~ ~ ~ ~ properly by software to get stabilization time which is longer than 20ms. by software ~ ~ oscillator (x in pin) ~ ~ n 0 bit counter n+1 n+2 n+4 ~ ~ normal operation stop operation normal operation 1 fe ff 0 12 ~ ~ ~ ~ ~ ~ t st > 62.5ms internal clock clear stop instruction executed ~ ~ ~ ~ ~ ~ at 4.19mhz by hardware ~ ~ reset n+3 t st = x 256 f main ? 1024 1 ~ ~ ~ ~
gms81c5108 42 june 2001 ver 1.0 minimizing current consumption the stop mode is designed to reduce power consumption. to minimize current drawn during stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. note: in the stop operation, the power dissipation asso- ciated with the oscillator and the internal hardware is low- ered; however, the power dissipation associated with the pin interface (depending on the external circuitry and pro- gram) is not directly determined by the hardware operation of the stop feature. this point should be little current flows when the input level is stable at the power voltage level (v dd /v ss ); however, when the input level becomes higher than the power voltage level (by approximately 0.3v), a cur- rent begins to flow. therefore, if cutting off the output tran- sistor at an i/o port puts the pin signal into the high- impedance state, a current flow across the ports input tran- sistor, requiring it to fix the level by pull-up or other means. it should be set properly that current flow through port doesn't exist. first consider the setting to input mode. be sure that there is no current flow after considering its relationship with external circuit. in input mode, the pin impedance viewing from external mcu is very high that the current doesnt flow. but input voltage level should be v ss or v dd . be careful that if unspecified voltage, i.e. if unfirmed voltage level (not v ss or v dd ) is applied to input pin, there can be little current (max. 1ma at around 2v) flow. if it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. setting to high or low is decided considering its relationship with external circuit. for example, if there is external pull-up re- sistor then it is set to output mode, i.e. to high, and if there is external pull-saving register, it is set to low. figure 10-10 application example of unused input port figure 10-11 application example of unused output port input pin v dd gnd i v dd x weak pull-up current flows v dd internal pull-up input pin i v dd x very weak current flows v dd o o open open i=0 o i=0 o gnd when port is configured as an input, input level should be closed to 0v or v dd to avoid power consumption. output pin gnd i in the left case, much current flows from port to gnd. x on off output pin gnd i in the left case, tr. base current flows from port to gnd. i=0 x off on v dd l on off open gnd v dd l on off to avoid power consumption, there should be low output on off o o v dd o to the port.
gms81c5108 june 2001 ver 1.0 43 11. basic interval timer the gms81c5108 has one 8-bit basic interval timer that is free-run and can not stop. block diagram is shown in figure 11-1. the basic interval timer register (bitr) is increased ev- ery internal count pulse which is divided by prescaler. since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. after reset, the bck bits are all set, so the longest oscillation stabiliza- tion time is obtained. it also provides a basic interval timer interrupt (bitf). the count overflow of bitr from ff h to 00 h causes the interrupt to be generated. the basic interval timer is con- trolled by the clock control register (ckctlr) shown in figure 11-2. source clock can be selected by lower 3 bits of ckctlr. when write 1 to bit bcl of ckctlr, bitr register is cleared to 0 and restart to count up. the bit bcl be- comes 0 automatically after one machine cycle by hard- ware. bitr and ckctlr are located at same address, and ad- dress 0f4 h is read as a bitr, and written to ckctlr. figure 11-1 block diagram of basic interval timer table 11-1 basic interval timer interrupt time mux basic interval timer interrupt bitr select input clock 3 basic interval timer source clock 8-bit up-counter bck<2:0> bcl f main ? 2 10 or f sub ? 2 10 f main ? 2 9 or f sub ? 2 9 f main ? 2 8 or f sub ? 2 8 f main ? 2 7 or f sub ? 2 7 f main ? 2 6 or f sub ? 2 6 f main ? 2 5 or f sub ? 2 5 f main ? 2 4 or f sub ? 2 4 f main ? 2 3 or f sub ? 2 3 ckctlr clear overflow internal bus line clock control register [0f4 h ] [0f4 h ] bitf f main : main-clock frequency f sub : sub-clock frequency bck <2:0> source clock interrupt (overflow) period scm r[1:0]= 00 or 01 scm r[1:0]= 10 or 11 at f main =4mhz at f sub =32.768khz 000 001 010 011 100 101 110 111 f main ? 2 3 f main ? 2 4 f main ? 2 5 f main ? 2 6 f main ? 2 7 f main ? 2 8 f main ? 2 9 f main ? 2 10 f sub ? 2 3 f sub ? 2 4 f sub ? 2 5 f sub ? 2 6 f sub ? 2 7 f sub ? 2 8 f sub ? 2 9 f sub ? 2 10 0.512 1.024 2.048 4.096 8.192 16.384 32.768 65.536 ms 62.5 125.0 250.0 500.0 1000.0 2000.0 4000.0 8000.0 ms
gms81c5108 44 june 2001 ver 1.0 figure 11-2 bitr: basic interval timer mode register example 1 : interrupt request flag is generated every 8.192ms at 4mhz. : ldm ckctlr,#0ch set1 bite ei : bcl 76543210 - - - bck1 basic interval timer source clock select 000: f main ? 2 3 001: f main ? 2 4 010: f main ? 2 5 011: f main ? 2 6 100: f main ? 2 7 101: f main ? 2 8 110: f main ? 2 9 111: f main ? 2 10 clear bit 0: normal operation (free-run) 1: clear 8-bit counter (bitr) to "0". this bit becomes 0 automatically initial value: ----0111 b address: 0f4 h after one machine cycle. ckctlr 76543210 initial value: 00 h address: 0f4 h bitr both register are in same address, when write, to be a ckctlr, when read, to be a bitr. caution: 8-bit binary counter - f main : main-clock frequency f sub : sub-clock frequency bck0 bck2 or f sub ? 2 4 or f sub ? 2 3 or f sub ? 2 6 or f sub ? 2 5 or f sub ? 2 7 or f sub ? 2 9 or f sub ? 2 8 or f sub ? 2 10
gms81c5108 june 2001 ver 1.0 45 12. timer / counter timer/event counter consists of prescaler, multiplexer, 8- bit timer data register, 8-bit counter register, mode register, input capture register and comparator as shown in figure 12-3. and the pwm high register for pwm is consisted separately. the timer/counter has seven operating modes. - 8 bit timer/counter mode - 8 bit capture mode - 8 bit compare output mode - 16 bit timer/counter mode - 16 bit capture mode - 16 bit compare output mode - pwm mode in the timer function, the register is increased every in- ternal clock input. thus, one can think of it as counting in- ternal clock input. since a least clock consists of 2 and most clock consists of 1024 oscillator periods, the count rate is 1/2 to 1/1024 of the oscillator frequency in timer0. and timer1 can use the same clock source too. in addition, timer1 has more fast clock source (1/1 to 1/8). in the counter function, the register is increased in re- sponse to a 0-to-1 (rising edge) transition at its correspond- ing external input pin ec0 (timer 0). in addition the capture function, the register is increased in response external interrupt same with timer function. when external interrupt edge input, the count register is captured into capture data register cdrx. timer1 is shared with pwm function and compare output function. example 1: timer 0 = 8-bit timer mode, 8ms interval at 4mhz timer 1 = 8-bit timer mode, 4ms interval at 4mhz ldm scmr,#0 ;main clock mode ldm tdr0,#249 ldm tm0,#0001_0011b ldm tdr1,#124 ldm tm1,#0000_1111b set1 t0e set1 t1e ei : : : example 2: timer0 = 16-bit timer mode, 0.5s at 4mhz ldm scmr,#0 ;main clock mode ldm tdr0,#23h ldm tdr1,#0f4h ldm tm0,#0fh ;f main /32, 8us ldm tm1,#4ch set1 t0e ei : : : example 3: timer0 = 8-bit event counter, 2ms interval at 4mhz timer1 = 8-bit capture mode, 2us sampling count. ldm tdr0,#99 ;99+1, 100 count ldm tm0,#01fh ;event counter ldm r0dr,#xxxx_1xxxb ;r03input ldm iesr,#xxxx_01xxb ;falling ldm pmr,#xxxx_1x1xb ;ec0,int1 ldm tdr1,#0ffh ldm tm1,#0001_1011b ;2us set1 t0e;enable timer 0 set1 t1e;enable timer 1 set1 int1e;enable ext. int1 ei : x: dont care. example 4: timer0 = 16-bit capture mode, 8us sampling count. at 4mhz ldm tdr0,#0ffh ldm tdr1,#0ffh ldm tm0,#02fh ldm tm1,#04fh ldm iesr,#xxxx_xx01b ldm pmr,#xxxx_xxx1b ;as int0 set1 t0e;enable timer 0 set1 int0e;enable ext. int0 ei : x: dont care.
gms81c5108 46 june 2001 ver 1.0 figure 12-1 timer0,1 registers t0ck2 bit : 7 6 5 4 3 2 1 0 cap0 - - t0ck[2:0] (timer 0 input clock selection) 111: external event clock (ec0) t0cn (timer 0 continue start) 0: stop counting 1: start counting t0st (timer 0 start control) 0: stop counting 1: clear the counter and start count again reserved initial value:--000000 b address: 0e0 h tm0 (timer0 mode register) r/w r/w r/w r/w t0cn t0st t0ck1 t0ck0 r/w r/w cap0 (capture mode selection bit) 0: capture disable 1: capture enable cap1 bit : 7 6 5 4 3 2 1 0 pwme t1ck[1:0] (timer 1 input clock selection) 11: timer 0 clock t1cn (timer 1 continue start) 0: stop counting 1: start counting t1st (timer 1 start control) 0: stop counting 1: clear the counter and start count again initial value:00000000 b address: 0e2 h tm1 (timer1 mode register) r/w r/w r/w r/w t1cn t1st t1ck1 t1ck0 r/w r/w pol (pwm output polarity selection) 0: duty active low 1: duty active high pol 16bit r/w r/w cap1 (capture mode selection bit) 0: capture disable 1: capture enable pwme (pwm enable bit) 0: pwm disable 1: pwm enable 16bit (16 bit mode selection) 0: 8-bit mode 1: 16-bit mode **the counter will be cleared and restarted only when the txst bit cleared and set again. if txst bit set again when txst bit is set, the counter cant be cleared but only start again. 000: f main ? 2 001: f main ? 2 2 010: f main ? 2 3 011: f main ? 2 5 100: f main ? 2 7 101: f main ? 2 9 110: f main ? 2 10 f main : main-clock frequency f sub : sub-clock frequency or f sub ? 2 2 or f sub ? 2 or f sub ? 2 5 or f sub ? 2 3 or f sub ? 2 7 or f sub ? 2 10 or f sub ? 2 9 00: f main 01: f main ? 2 10: f main ? 2 3 or f sub ? 2 or f sub or f sub ? 2 3
gms81c5108 june 2001 ver 1.0 47 figure 12-2 related registers with timer/counter cdr0 (input capture register) t0 (timer 0 counter register) cdr04 bit : 7 6 5 4 3 2 1 0 cdr05 initial value:00h address: e1 h rrrr cdr01 cdr00 cdr03 cdr02 rr in timer mode, this register is the value of timer 0 counter and in capture mode, this register is the value of input capture. cdr07 cdr06 rr tdr0 (timer 0 data register) tdr04 bit : 7 6 5 4 3 2 1 0 tdr05 initial value:ff h address: 0e1 h wwww tdr01 tdr00 tdr03 tdr02 ww if the counter of timer 0 and the data of tdr0 is equal, interrupt is occurred. tdr07 tdr06 ww cdr1 (input capture register) t1 (timer 1 counter register) cdr14 bit : 7 6 5 4 3 2 1 0 cdr15 initial value:00 h address: 0e4 h rrrr cdr11 cdr10 cdr13 cdr12 rr in timer mode, this register is the value of timer 1 counter and in capture mode, this register is the value of input capture. cdr17 cdr16 rr tdr1 (timer 1 data register) tdr14 bit : 7 6 5 4 3 2 1 0 tdr15 initial value:ff h address: 0e3 h wwww tdr11 tdr10 tdr13 tdr12 ww if the counter of timer 1 and the data of tdr1 is equal, interrupt is occurred. tdr17 tdr16 ww t1ppr (timer 1 pulse period register) t1ppr4 bit : 7 6 5 4 3 2 1 0 t1ppr5 initial value:ff h address: 0e3 h wwww t1ppr1 t1ppr0 t1ppr3 t1ppr2 ww the period is decided by pwm. t1ppr7 t1ppr6 ww t1pdr (timer 1 pulse duty register) t1pdr4 bit : 7 6 5 4 3 2 1 0 t1pdr5 initial value:00 h address: 0e4 h w/r w/r w/r w/r t1pdr1 t1pdr0 t1pdr3 t1pdr2 w/r w/r in pwm mode, decide the pulse duty. t1pdr7 t1pdr6 w/r w/r pwmhr (pwm high register) - bit : 7 6 5 4 3 2 1 0 - initial value:----0000 b address: 0e5 h wwww pwm01 pwm00 pwm03 pwm02 pwm period = [pwmhr[3:2] + t1ppr] x source clock -- reserved pwm duty = [pwmhr[1:0] + t1pdr] x source clock
gms81c5108 48 june 2001 ver 1.0 table 12-1 operating modes of timer 0 and timer 1 12.1 8-bit timer/counter mode the gms81c5108 has two 8-bit timer/counters, timer 0, timer 1, as shown in figure 12-3. the timer or counter function is selected by mode reg- isters tmx as shown in figure 12-1 and table 12-1. to use as an 8-bit timer/counter mode, bit cap0 of tm0 is cleared to 0 and bits 16bit of tm1 should be cleared to 0 (table 12-1 ). figure 12-3 block diagram of timer/event counter 16bit cap0 cap1 pwme t0ck[2:0] t1ck[1:0] pwmo timer 0 timer 1 0 0 0 0 xxx xx 0 8 bit timer 8 bit timer 0 0 1 0 111 xx 0 8 bit event counter 8 bit capture 0 1 0 0 xxx xx 1 8 bit capture 8 bit compare output 0 0 0 1 xxx xx 1 8 bit timer/counter 10 bit pwm 1 0 0 0 xxx 11 0 16 bit timer 1 0 0 0 111 11 0 16 bit event counter 11 x 1 0 xxx 11 0 16 bit capture 1 0 0 0 xxx 11 1 16 bit compare output 1. x: the value 0 or 1 corresponding your operation . ? 1 ? 2 ? 8 tm0 address : 0e0 h reset value : --000000 b - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st tm1 address : 0e2 h reset value : 00000000 b pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st 0xxxxx x0 0 0xxxx ? 2 ? 4 ? 128 ? 512 ? 8 ? 32 ec0 edge detector mux mux 1 1 t0 (8-bit) tdr0 (8-bit) t0if clear comparator timer 0 interrupt t1 (8-bit) tdr1 (8-bit) t1if clear comparator timer 1 interrupt t0st 0 : stop 1 : clear and start t1st 0 : stop 1 : clear and start t0cn t1cn t0ck[2:0] t1ck[1:0] f/f compo pin (r31) ? 1024 x : the value 0 or 1 corresponding your operation. pwmo [pmr.6] sx in 0x 1x x in scmr[1:0] 2
gms81c5108 june 2001 ver 1.0 49 these timers have each 8-bit count register and data regis- ter. the count register is increased by every internal or ex- ternal clock input. the internal clock has a prescaler divide ratio option of 2, 4, 8, 32,128, 512, 1024 (selected by con- trol bits t0ck2, t0ck1 and t0ck0 of register tm0) and 1, 2, 8 (selected by control bits t1ck1 and t1ck0 of reg- ister tm1). in the timer, timer register t x increases from 00 h until it matches tdr x and then reset to 00 h . if the value of t x is equal with tdr x , timer x interrupt is occurred (latched in t x if bit). tdr0 and t0 register are in same address, so this register is read from t0 and written to tdr0. in counter function, the counter is increased every 0-to 1 (rising edge) transition of ec0 pin. in order to use counter function, the bit r03 of the r0 direction register (r0dr) should be set to 0 and the bit ec0 of port mode register (pmr) should set to 1. the timer 0 can be used as a counter by pin ec0 input, but timer 1 can not used as a counter. note: the contents of tdr0 and tdr1 must be initialized (by software) with the value between 1 h and 0ff h , not 0 h . figure 12-4 counting example of timer data registers figure 12-5 timer count operation ~ ~ timer 0 (t0if) interrupt tdr0 time occur interrupt occur interrupt occur interrupt interrupt period u p -c o u n t ~ ~ ~ ~ 0 1 2 3 4 5 6 7 8 9 n n-1 p cp = p cp x (n+1) timer 0 (t0if) interrupt tdr0 time occur interrupt occur interrupt stop clear & start disable enable start & stop t0st t0cn control count u p - c o u n t ~ ~ ~ ~ t0st = 0 t0st = 1 t0cn = 0 t0cn = 1
gms81c5108 50 june 2001 ver 1.0 12.2 16 bit timer/counter mode the timer register is running with 16 bits. a 16-bit timer/ counter register t0, t1 are increased from 0000 h until it matches tdr0, tdr1 and then resets to 0000 h . the match output generates timer 0 interrupt not timer 1 in- terrupt. the clock source of the timer 0 is selected either internal or external clock by bit t0ck2, t0ck1 and t0ck0. in 16-bit mode, the bits t1ck1,t1ck0 and 16bit of tm1 should be set to 1 respectively. figure 12-6 16-bit timer / counter mode 12.3 8-bit capture mode the timer 0 capture mode is set by bit cap0 of timer mode register tm0 (bit cap1 of timer mode register tm1 for timer 1) as shown in figure 12-7. as mentioned above, not only timer 0 but timer 1 can also be used as a capture mode. the timer/counter register is increased in response inter- nal or external input. this counting function is same with normal timer mode, and timer interrupt is generated when timer register t0 (t1) increases and matches tdr0 (tdr1). this timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of timer. for example, in figure 12-9, the pulse width of captured signal is wider than the timer data value (ff h ) over 2 times. when external interrupt is occurred, the captured value (13 h ) is more little than wanted value. it can be ob- tained correct value by counting the number of timer over- flow occurrence. timer/counter still does the above, but with the added fea- ture that a edge transition at external input intx pin causes the current value in the timer x register (t0,t1), to be cap- tured into registers cdrx (cdr0, cdr1), respectively. after captured, timer x register is cleared and restarts by hardware. it has three transition modes: falling edge, rising edge, both edge which are selected by interrupt edge selection register iesr (refer to external interrupt section). in addi- tion, the transition at intx pin generate an interrupt. note: the cdr0, tdr0 and t0 are in same address. in the capture mode, reading operation is read the cdr0 and in timer mode, reading operation is read the t0. tdr0 is only for writing operation. the cdr1, t1 are in same address, the tdr1 is lo- cated in different address. in the capture mode, reading operation is read the cdr1 tm0 address : 0e0 h reset value : --000000 b - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st tm1 address : 0e2 h reset value : 00000000 b pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st 0xxxxx x10011xx ? 2 ? 4 ? 128 ? 512 ? 8 ? 32 ec0 edge detector mux 1 t1 (8-bit) tdr1 (8-bit) t0if clear comparator timer 0 interrupt t0 (8-bit) tdr0 (8-bit) t0st 0 : stop 1 : clear and start t0cn t0ck[2:0] f/f compo (r31) ? 1024 x : the value 0 or 1 corresponding your operation. sx in 0x 1x x in scmr[1:0] 2 pwmo [pmr.6]
gms81c5108 june 2001 ver 1.0 51 figure 12-7 8-bit capture mode ? 1 ? 2 ? 8 tm0 address : 0e0h reset value : --000000 b - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st tm1 address : 0e2h reset value : 00000000 b pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st 1xxxxx x001xxxx ? 2 ? 4 ? 128 ? 512 ? 8 ? 32 ec0 edge detector mux mux 1 1 t0 (8-bit) cdr0 (8-bit) t0if clear comparator timer 0 interrupt t0st 0 : stop 1 : clear and start t0cn t1cn t0ck[2:0] t1ck[1:0] tdr0 (8-bit) int0if int 0 interrupt int0 t1 (8-bit) cdr1 (8-bit) t1if clear comparator timer 1 interrupt tdr1 (8-bit) int1if int 1 interrupt int1 t0st 0 : stop 1 : clear and start iesr[1:0] iesr[3:2] capture capture ? 1024 sx in 0x 1x x in scmr[1:0] 2
gms81c5108 52 june 2001 ver 1.0 figure 12-8 input capture operation figure 12-9 excess timer overflow in capture mode ~ ~ ext. int0 pin interrupt request t0 time u p - cou n t ~ ~ ~ ~ 0 1 2 3 4 5 6 7 8 9 n n-1 capture (timer stop) clear & start interrupt interval period delay (int0if) ext. int0 pin interrupt request (int0if) this value is loaded to cdr0 interrupt interval period = ff h + 01 h + ff h +01 h + 13 h = 213 h ff h ff h ext. int0 pin interrupt request (int0if) 00 h 00 h interrupt request (t0if) t0 13 h
gms81c5108 june 2001 ver 1.0 53 12.4 16-bit capture mode 16-bit capture mode is the same as 8-bit capture, except that the timer register is running with 16 bits. the clock source of the timer 0 is selected either internal or external clock by bit t0ck2, t0ck1 and t0ck0. in 16-bit mode, the bits t1ck1,t1ck0 and 16bit of tm1 should be set to 1 respectively. figure 12-10 16-bit capture mode 12.5 8-bit (16-bit) compare output mode the gms81c5108 has a function of timer compare out- put. to pulse out, the timer match can goes to port pin (r31) as shown in figure 12-3 and figure 12-6. thus, pulse out is generated by the timer match. these operation is implemented to pin, r31/pwm. in this mode, the bit pwmo of port mode register (pmr) should be set to 1, and the bit pwme of timer1 mode register (tm1) should be cleared to 0. in addition, 16-bit compare output mode is available, also. this pin output the signal having a 50 : 50 duty square wave, and output frequency is same as below equation. 12.6 pwm mode the gms81c5108 has one high speed pwm (pulse width modulation) function which shared with timer1. in pwm mode, the r31/pwm pin operates as a 10-bit res- olution pwm output port. for this mode, the bit pwm of port mode register (pmr) and the bit pwme of timer1 mode register (tm1) should be set to 1 respectively. the period of the pwm output is determined by the t1ppr (pwm period register) and pwmhr[3:2] (bit3,2 of pwm high register) and the duty of the pwm output is determined by the t1pdr (pwm duty register) and pwmhr[1:0] (bit1,0 of pwm high register). the user can use pwm data by writing the lower 8-bit pe- riod value to the t1ppr and the higher 2-bit period value to the pwmhr[3:2]. and the duty value can be used with the t1pdr and the pwmhr[1:0] in the same way. the t1pdr is configured as a double buffering for glitch- tm0 address : 0e0h reset value : --000000 b - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st tm1 address : 0e2h reset value : 00000000 b pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st 1xxxxx x10x11xx ? 2 ? 4 ? 128 ? 512 ? 8 ? 32 ec0 edge detector mux 1 t0 + t1 (16-bit) tdr1 t0if clear comparator timer 0 interrupt t0st 0 : stop 1 : clear and start t0cn t0ck[2:0] tdr0 int0if int 0 interrupt int0 iesr[1:0] capture cdr1 cdr0 (8-bit) (8-bit) (8-bit) (8-bit) ? 1024 x : the value 0 or 1 corresponding your operation. sx in 0x 1x x in scmr[1:0] 2 f comp oscillation frequency 2 prescaler value tdr 1 ) + ( -------------------------------------------------------------------------------------- =
gms81c5108 54 june 2001 ver 1.0 less pwm output. in figure 12-11, the duty data is trans- ferred from the master to the slave when the period data matched to the counted value. (i.e. at the beginning of next duty cycle). the bit pol0 of tm1 decides the polarity of duty cycle. the duty value can be changed when the pwm outputs. however the changed duty value is output after the current period is over. and it can be maintained the duty value at present output when changed only period value shown as figure 12-13. as it were, the absolute duty time is not changed in varying frequency. note: if the user need to change mode from the timer1 mode to the pwm mode, the timer1 should be stopped firstly, and then set period and duty register value. if user writes register values and changes mode to pwm mode while timer1 is in operation, the pwm data would be different from expected data in the beginning. the relation of frequency and resolution is in inverse pro- portion. table 12-2 shows the relation of pwm frequency vs. resolution. pwm period = [pwmhr[3:2]t1ppr+1] x source clock pwm duty = [pwmhr[1:0]t1pdr+1] x source clock if it needed more higher frequency of pwm, it should be reduced resolution. note: if the duty value and the period value are same, the pwm output is determined by the bit pol0 (1: high, 0: low). and if the duty value is set to 00 h , the pwm output is determined by the bit pol0(1: low, 0: high). the period value must be same or more than the duty value, and 00 h cannot be used as the period value. table 12-2 pwm frequency vs. resolution at 4mhz figure 12-11 pwm mode resolution frequency t1ck[1:0] =00 (250ns) t1ck[1:0] =01 (500ns) t1ck[1:0] =10 (2us) 10-bit 3.9khz 1.95khz 0.49khz 9-bit 7.8khz 3.9khz 0.98khz 8-bit 15.6khz 7.8khz 1.95khz 7-bit 31.25khz 15.6khz 3.90khz ? 1 ? 2 ? 8 pwmhr address : 0e5 h reset value : ----0000 b - - - - pwm03 pwm02 pwm01 pwm00 xxxx mux 1 t1cn t1ck[1:0] t1 (8-bit) t1st 0 : stop 1 : clear and start clear comparator comparator t1pdr (8-bit) pwmhr[1:0] t1ppr (8-bit) pwmhr[3:2] t1pdr (8-bit) sq r pol pwmo r31/pwm t0 clock source tm1 address : 0e2 h reset value : 00 h pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st x010xxxx [pmr.6] period high duty high slave master bit manipulation not available x : the value 0 or 1 corresponding your operation. sx in 0x 1x x in scmr[1:0] 2
gms81c5108 june 2001 ver 1.0 55 figure 12-12 example of pwm at 4mhz figure 12-13 example of changing the period in absolute duty cycle (@4mhz) example: timer1 @4mhz, 4khz - 20 % duty pwm mode ldm r3dr,#0000_xx1xb ;r31 output ldm tm1,#0010_0000b ;pwm enable ldm t1pwhr,#0000_1100b ;20% duty ldm t1ppr,#1110_0111b ;period 250us ldm t1pdr,#1100_0111b ;duty 50us ldm rsr,#x1xx_xxxxb ;set pwm port. ldm tm1,#0010_0011b ;timer1 start x means dont care fxin t1 pwm ~ ~ ~ ~ ~ ~ 01 02 03 04 7f 80 81 3ff 01 02 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ pol=1 pwm pol=0 duty cycle [80 h +1 x 250ns = 32.25us] period cycle [3ff h x 250ns = 256us, 3.9khz] pwmhr = 0c h t1ppr = ff h t1pdr = 80 h t1ck[1:0] = 00 (250ns) pwm03 pwm02 pwm01 pwm00 t1ppr (8-bit) t1pdr (8-bit) period duty 11 ff h 00 80 h 00 00 source t1 pwm pol=1 duty cycle period cycle [0d h +1 x 2us = 28us, 35.7khz] pwmhr = 00 h t1ppr = 0d h t1pdr = 04 h t1ck[1:0] = 10 (2us) 00 01 02 03 04 05 07 08 0a 0b 0c 0d 00 01 02 03 04 05 06 07 08 09 00 01 02 03 06 09 04 [04 h +1 x 2us = 10us] duty cycle [04 h +1 x 2us = 10us] period cycle [09 h +1 x 2us = 20us, 50khz] duty cycle [04 h +1 x 2us = 10us] write t1ppr to 09 h period changed clock
gms81c5108 56 june 2001 ver 1.0 13. watch timer/watch dog timer this has two functions, one is the interrupt occurrence for watch time and the other is the signal generation of wdtoutb for watch dog. 13.1 watch timer the watch timer consists of the clock selector, 21-bit bina- ry counter and watch timer mode register. it is a multi-pur- pose timer. it is generally used for watch design. the bit 1,2 of wtmr select the clock source of watch tim- er among sub-clock, f main ? 2 7 of main-clock and f main of main-clock. the f main of main-clock is used usually for watch timer test, so generally it is not used for the clock source of watch timer. the f main ? 2 7 of main-clock is used when the single clock system is organized. in f main ? 2 7 clock source, if the cpu enters into stop mode, the main- clock is stopped and then watch timer is also stopped. if the sub-clock is the source clock, the watch timer count cannot be stopped. therefore, the sub-clock does not stop but con- tinues to oscillate even when the cpu is in the stop mode. the timer counter consists of 21-bit binary counter and it can count to max 64 seconds at sub-clock. the bit 2, 3 of wtmr select the interrupt request interval of watch timer among 2hz, 4hz, 16hz and 1/64hz. figure 13-1 watch timer mode register figure 13-2 watch timer block diagram wdtcl bit : 7 6 5 4 3 2 1 0 wdten wtin[1:0] (watch timer interrupt interval selection) 00: 16hz 01: 4hz 10: 2hz 11: 1/64hz wdten (watch dog timer enable bit) 0: watch dog timer disable 1: watch dog timer enable initial value:-0000000 b address: 0ef h wtmr (watch timer mode register) r/w r/w r/w r/w wtck1 wtck0 wtin1 wtin0 r/w r/w wten (watch timer enable bit) 0: watch timer disable 1: watch timer enable -wten r/w wtck[1:0] (watch timer clock source selection) 00: sub. clock (f sub ) wdtcl (watch dog timer clear bit) 0: timer running 1: wdt clear (auto reset after 1 cycle) 01: main clock (f main ? 2 7 ) 10: main clock (f main ) 11: - * when f sub = 32.768 khz and f main = 4.19 mhz mux f sub wdtcl f main 21 bit 2 bit 16 hz watch timer f main ? ? ? ? 2 7 wtck[1:0] binary counter 4 hz 2 hz 1/64 hz mux wtin[1:0] wten wtif interrupt f/f wdten wdtout
gms81c5108 june 2001 ver 1.0 57 13.2 watch dog timer the watch dog timer (wdt) function is used for checking program malfunction. if the watch dog timer is not reset in a fixed time, the wdtoutb pin outputs a low signal. therefore, by connecting the wdtoutb pin and the reset pin externally, the mcu can be reset when the malfunction is occurred. usually the stop mode is used to reduce the power con- sumption. when the stop mode is released by watch timer interrupt, it is recommend to set the wdtcl to clear the 2-bit counter and enter the stop mode. if the clock source is 1/64hz, the wdtcl cannot be cleared in 500ms. in this case, the user should disable the wdt by clearing the wdten or disconnect the wdtoutb pin and reset pin. usage of watch timer in stop mode when the system is off and the watch should be kept work- ing, follow the steps below. 1. determines which mode is to be performed between main mode and sub mode when the mcu is released from stop mode and set the clock source of watch timer to sub-clock. 2. enters in stop mode. 3. after released by watch timer interrupt, counts up timer and refreshes lcd display. when the performing count up and refresh the lcd, the cpu operates either in main frequency mode or sub frequency mode. 4. enters in stop mode again. 5. repeats 3 and 4. when using stop mode, if the watch timer interrupt inter- val is selected to 2hz, the power consumption can be reduced considerably. fw/211 (16hz) intwt (16hz) 500msec wdtcl 500msec if the wdtcl is not cleared during this interval, the wdtoutb will be low during next interval. the wdtcl should be set during this interval. the wdtcl should be set during this interval. fw/213 (4hz) fw/214 (2hz) intwt (4hz) intwt (2hz) wdt reset signal wdtoutb
gms81c5108 58 june 2001 ver 1.0 14. analog to digital converter the analog-to-digital converter (a/d) allows conversion of an analog input signal to a corresponding 8-bit digital value. the a/d module has four analog inputs, which are multiplexed into one sample and hold. the output of the sample and hold is the input into the converter, which gen- erates the result via successive approximation. the analog supply voltage is connected to av dd of ladder resistance of a/d module. the a/d module has two registers which are the a/d mode register (admr) and a/d data register (addr). the admr register, shown in figure 14-1, controls the opera- tion of the a/d converter module. the port pins can be configured as analog inputs or digital i/o. to use analog inputs, each port should be assigned analog input port by setting input mode by r2dr direction register. and select the corresponding channel to be converted by setting adan[1:0]. the processing of conversion is start when the start bit adst is set to 1. after one cycle, it is cleared by hard- ware. the register addr contains the result of the a/d conversion. when the conversion is completed, the result is loaded into the addr, the a/d conversion status bit adf is set to 1, and the a/d interrupt flag adif is set. the block diagram of the a/d module is shown in figure 14-1. the a/d status bit adf is automatically set when a/ d conversion is completed, cleared when a/d conversion is in process. the conversion time takes maximum 30 us (at f main = 4mhz). figure 14-1 a/d converter block diagram & registers av dd r20/an0 r21/an1 r22/an2 r23/an3 anen 00 01 10 11 s/h successive approximation circuit adif resistor ladder circuit adan[1:0] addr (8-bit) sample & hold a/d interrupt address : 0ed h reset value : undefined a/d converter data register anen anen anen anen admr (a/d mode register) address : 0ec h reset value : -0--0001 b - aden - - adan1 adan0 adst adf adf (a/d status bit) 0 : a/d conversion is in process 1 : a/d conversion is completed adst (a/d start bit) 1 : a/d conversion is started after 1 cycle, cleared to 0 0 : bit force to zero 00 : channel 0 (r20/an0) 01 : channel 1 (r21/an1) 10 : channel 2 (r22/an2) 11 : channel 3 (r23/an3) aden (a/d converter enable bit) 1 : enable 0 : disable addr (a/d data register) address : 0ed h reset value : undefined add7 add6 add5 add4 add3 add2 add1 add0 adan[1:0] (a/d converter input selection) bit : 7 6 5 4 3 2 1 0 r/w r/w r/w r r/w bit : 7 6 5 4 3 2 1 0 rrrr rrr r comparator
gms81c5108 june 2001 ver 1.0 59 figure 14-2 a/d converter operation flow a/d converter cautions (1) input range of an0 to an3 the input voltages of an0 to an3 should be within the specification range. in particular, if a voltage above av dd or below v ss is input (even if within the absolute maxi- mum rating range), the conversion value for that channel can not be indeterminated. the conversion values of the other channels may also be affected. (2) noise countermeasures in order to maintain 8-bit resolution, attention must be paid to noise on pins av dd and an0 to an3. since the effect increases in proportion to the output impedance of the an- alog input source, it is recommended that a capacitor is connected externally as shown below in order to reduce noise . figure 14-3 analog input pin connecting capacitor (3) pins an0/r20 to an3/r23 the analog input pins an0 to an3 also function as input/ output port (port r2) pins. when a/d conversion is per- formed with any of pins an0 to an3 selected, be sure not to execute a port input instruction while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. (4) av dd pin input impedance a series resistor string of approximately 10k w is connect- ed between the av dd pin and the v ss pin. therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the av dd pin and the v ss pin, and there will be a large reference voltage error. enable a/d converter a/d start (adst = 1) nop adf = 1 a/d input channel select read addr yes no analog reference select an0~an3 100~1000pf analog input
gms81c5108 60 june 2001 ver 1.0 15. buzzer output function the buzzer driver consists of 6-bit binary counter, the buzzer data register bdr and the clock selector. it gener- ates square-wave which is very wide range frequency (500 hz~125 khz at f main = 4mhz) by user programmable counter. pin r04 is assigned for output port of buzzer driver by set- ting the bit buz of port mode register (pmr) to 1. the 6-bit buzzer counter is cleared and start the counting by writing signal to the register bdr. it is increased from 00 h until it matches with bdr[5:0]. also, it is cleared by counter overflow and count up to out- put the square wave pulse of duty 50%. the bit 0 to 5 of bdr determines output frequency for buzzer driving. bcd is undefined after reset, so it must be initialized to between 0 h and 3f h by software. note that bdr is a write-only register. frequency calculation is fol- lowing as shown below. the bits bck1, bck0 of bdr select the source clock from prescaler output f buz : buz pin frequency prescaler ratio: prescaler divide ratio by bdr[7:6] bcd value: 6-bit compare data, bcd[5:0]. figure 15-1 buzzer driver example: 2.5khz output at 4mhz. ldm r0dr,#xxx1_xxxxb ldm bdr,#1001_1000b ldm pmr,#xxx1_xxxxb ;buzzer on x means dont care f buz hz () oscillator frequency 2 prescaler ratio bcd 1 + () ------------------------------------------------------------------------------ - = bdr (buzzer data register) address : 0fd h reset value : 00 h bck1 bck0 bcd5 bcd4 bcd3 bcd2 bcd1 bcd0 ? 64 ? 16 ? 32 mux counter (6-bit) bcd (6-bit) f/f comparator bck[1:0] r04/buz pin ? 8 bck[1:0] (buzzer clock source) bcd[5:0] (buzzer control data) buz [pmr.4] bit manipulation is not available. buzzer period data bit : 7 6 5 4 3 2 1 0 wwww www w sx in 0x 1x x in scmr[1:0] 2 pmr (port mode register) address :0d9 h reset value : -0-00000 b - pwmo - buz ec0 int2 int1 int0 buz (buzzer output) 0: r04 port (turn off buzzer) 1: buz port (turn on buzzer) 00: f main ? 2 3 01: f main ? 2 4 10: f main ? 2 5 11: f main ? 2 6 or f sub ? 2 4 or f sub ? 2 3 or f sub ? 2 6 or f sub ? 2 5
gms81c5108 june 2001 ver 1.0 61 buzzer output frequency when main-frequency is 4mhz, buzzer frequency is shown as below and if sub-frequency is selected as clock source, buzzer frequency is used after dividing by 128. table 15-1 buzzer output frequency bdr [5:0] frequency output (khz) bdr [5:0] frequency output (khz) 00 01 10 11 00 01 10 11 00 01 02 03 04 05 06 07 250.000 125.000 83.333 62.500 50.000 41.667 35.714 31.250 125.000 62.500 41.667 31.250 25.000 20.833 17.857 15.625 62.500 31.250 20.833 15.625 12.500 10.417 8.929 7.813 31.250 15.625 10.417 7.813 6.250 5.208 4.464 3.906 20 21 22 23 24 25 26 27 7.576 7.353 7.143 6.944 6.757 6.579 6.410 6.250 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 1.894 1.838 1.786 1.736 1.689 1.645 1.603 1.563 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 08 09 0a 0b 0c 0d 0e 0f 27.778 25.000 22.727 20.833 19.231 17.857 16.667 15.625 13.889 12.500 11.364 10.417 9.615 8.929 8.333 7.813 6.944 6.250 5.682 5.208 4.808 4.464 4.167 3.906 3.472 3.125 2.841 2.604 2.404 2.232 2.083 1.953 28 29 2a 2b 2c 2d 2e 2f 6.098 5.952 5.814 5.682 5.556 5.435 5.319 5.208 3.049 2.976 2.907 2.841 2.778 2.717 2.660 2.604 1.524 1.488 1.453 1.420 1.389 1.359 1.330 1.302 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 10 11 12 13 14 15 16 17 14.706 13.889 13.158 12.500 11.905 11.364 10.870 10.417 7.353 6.944 6.579 6.250 5.952 5.682 5.435 5.208 3.676 3.472 3.289 3.125 2.976 2.841 2.717 2.604 1.838 1.736 1.645 1.563 1.488 1.420 1.359 1.302 30 31 32 33 34 35 36 37 5.102 5.000 4.902 4.808 4.717 4.630 4.545 4.464 2.551 2.500 2.451 2.404 2.358 2.315 2.273 2.232 1.276 1.250 1.225 1.202 1.179 1.157 1.136 1.116 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 18 19 1a 1b 1c 1d 1e 1f 10.000 9.615 9.259 8.929 8.621 8.333 8.065 7.813 5.000 4.808 4.630 4.464 4.310 4.167 4.032 3.906 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.953 1.250 1.202 1.157 1.116 1.078 1.042 1.008 0.977 38 39 3a 3b 3c 3d 3e 3f 4.386 4.310 4.237 4.167 4.098 4.032 3.968 3.906 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.953 1.096 1.078 1.059 1.042 1.025 1.008 0.992 0.977 0.548 0.539 0.530 0.521 0.512 0.504 0.496 0.488
gms81c5108 62 june 2001 ver 1.0 16. serial communication interface the sci module allows 8-bits of data to be synchronously transmitted and received. this is useful for communication with other peripheral of microcontroller devices.this con- sists of serial i/o data register, serial i/o mode register, clock selection circuit octal counter and control circuit as shown in figure 16-1. figure 16-1 sci registers and block diagram siom (seriol i/o mode register) address : 0fe h reset value : 00000001 b pol msbs sio1 sio0 sick1 sick0 siost siosf siod (serial i/o data register) address : 0ff h reset value : undefined bit : 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w pol (polarity selection) 0 : data transmission at falling edge (received data latch at rising edge) 1 : data transmission at rising edge (received data latch at falling edge) sio[1:0] (serial i/o operation mode) 00 : normal port (r05, r06, r07) 01 : transmit mode (sck, so, r07) 10 : receive mode (sck, r06, si) 11 : transmit & receive mode (sck, so, si) siost (serial i/o operation start control) 0 : sio operation stop 1 : sio operation start (after one sck clock become 0) sick[1:0] (serial i/o clock source selection) 00: f main ? 4 01: f main ? 16 10: t0o (timer 0 output) 11: external clock msbs (msb first transmit and receive selection) 0 : lsb first 1 : msb first siosf (serial i/o status flag) 0 : during sio operation 1 : sio operation finished bit : 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w siod7 siod6 siod5 siod4 siod3 siod2 siod1 siod0 r06/so scmr[1:0] 2 0x 1x x in sx in pre- scaler sick[1:0] f main ? 2 2 or f sub ? 2 2 f main ? 2 4 or f sub ? 2 4 t0ov(timer 0 overflow) 2 00 01 10 11 r05 sck pol sio control circuit siost 1 sio[1:0] = 00 sick[1:0] 1 1 1 1 11 & sio[1:0] 1 1 1 1 00 1 0 msbs r07/si octal counter sio (3-bit) sioif interrupt siod(8-bit) sio[1] = 1 msbs 0 1 sio[0] = 1 msb lsb sck siosf sio data register start complete clock shift clock clear or f sub ? 4 or f sub ? 16
gms81c5108 june 2001 ver 1.0 63 to accomplish communication, typically three pins are used: - serial data in r07/si - serial data out r06/so - serial clock r05/sck the serial data transfer operation mode is decided by set- ting the sio1 and sio0 and the transfer clock rate is decid- ed by setting the sick1 and sick0 of sci mode control register as shown in figure 16-1. and the polarity of transfer clock is selected by setting the pol. the msbs bit is used to select which bit would be sending or receiv- ing. 16.1 data transmit/receive timing the sci operation is executed by setting the siost bit to 1. the siost bit is cleared to 0 automatically after 1 machine cycle. the serial output data is shift in or shift out at edge decided by pol. interrupt is occurred when the eight in/out datas is counted by octal counter. figure 16-2 sci timing diagram sio1 sio0 function selection port selection r05/sck r06/so r07/si 0 0 - r05 r06 r07 0 1 transmit mode sck so r07 1 0 receive mode sck r06 si 1 1 transmit and receive sck so si d1 d2 d3 d4 d6 d7 d0 d5 d1 d2 d3 d4 d6 d7 d0 d5 siost r05/sck (pol=1) r05/sck (pol=0) r06/so r07/si sioif (sci int. req) msbs=0 siosf
gms81c5108 64 june 2001 ver 1.0 16.2 the method of serial i/o 1. select transmission/receiving mode when external clock is used, the frequency should be less than 1mhz and recommended duty is 50%. 2. in case of sending mode, write data to be send to siod. 3. set siost to 1 to start serial transmission. if both transmission mode is selected and transmission is per- formed simultaneously it would be made error. 4. the sio interrupt is generated at the completion of sio and siosf is set to 1. 5. in case of receiving mode, the received data is acquired by reading the siod. figure 16-3 sci timing diagram at pol=1 d1 d2 d3 d4 d6 d7 d0 d5 d1 d2 d3 d4 d6 d7 d0 d5 siost sclk [r05] (pol=1) sout [r06] sin [r07] sioif siosf
gms81c5108 june 2001 ver 1.0 65 17. interrupts the gms81c5108 interrupt circuits consist of interrupt enable register (ienh, ienl), interrupt request flag (irqh, irql), interrupt edge selection register (iesr), priority circuit and master enable flag (i flag of psw). the configuration of interrupt circuit is shown in figure 17-1 and interrupt priority is shown in table 17-1 . the flags that actually generate these interrupts are bit int0f, int1f and int2f in register irqh. when an ex- ternal interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vec- tored to only if the interrupt was transition-activated. the timer 0 and timer 2 interrupts are generated by t0if and t1if, which are set by a match in their respective tim- er/counter register. the ad converter interrupt is generat- ed by adif which is set by finishing the analog to digital conversion. the basic interval timer interrupt is generat- ed by bitif which is set by overflow of the basic interval timer register (bitr). table 17-1 interrupt priority figure 17-1 block diagram of interrupt function reset/interrupt symbol priority vector addr. hardware reset key scan interrupt bit interrupt external interrupt 0 external interrupt 1 timer 0 interrupt timer 1 interrupt external interrupt 2 remocon interrupt ad interrupt sio interrupt watch timer interrupt reset ks bit int0 int1 t0 t1 int2 rem ad sio wt - 1 2 3 4 5 6 7 8 9 10 11 fffe h fffc h fffa h fff8 h fff6 h fff4 h fff2 h fff0 h ffee h ffec h ffea h ffe8 h bit sioif adif a/d converter remocon timer 1 timer 0 ext. int. 1 ext. int. 0 ienh interrupt enable interrupt enable irqh irql interrupt vector address generator internal bus line register (lower byte) internal bus line register (higher byte) release stop to cpu interrupt master enable flag i flag ienl priority control i-flag is in psw, it is cleared by di, set by ei instruction.when it goes interrupt service, i-flag is cleared by hardware, thus any other interrupt are inhibited. when interrupt service is completed by reti instruction, i-flag is set to 1 by hardware. ksif bitif int0if int1if remif 6 5 4 6 5 4 iesr toif t1if int2if 3 2 1 0 wt wtif 3 key scan ext. int. 2 sio
gms81c5108 66 june 2001 ver 1.0 the external interrupts int0, int1 and int2 can each be transition-activated (1-to-0, 0-to-1 and both transiton).the interrupts are controlled by the interrupt master enable flag i-flag (bit 2 of psw), the interrupt enable register (ienh, ienl) and the interrupt request flag (irqh, irql) except power-on reset and software brk interrupt. interrupt enable registers are shown in figure 17-2. these registers are composed of interrupt enable flags of each in- terrupt source, these flags determine whether an interrupt will be accepted or not. when enable flag is 0, a corre- sponding interrupt source is prohibited. note that psw contains also a master enable bit, i-flag, which disables all interrupts at once. when an interrupt is occurred, the i-flag is cleared and disable any further interrupt, the return ad- dress and psw are pushed into the stack and the pc is vec- tored to. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt request flag bits. the interrupt request flag bit(s) must be cleared by soft- ware before re-enabling interrupts to avoid recursive inter- rupts. the interrupt request flags are able to be read and written. figure 17-2 interrupt enable registers and interrupt request registers 17.1 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to 0 by a reset or an in- struction. interrupt acceptance sequence requires 8 f osc (2 m s at f main =4mhz) after the completion of the current in- struction execution. the interrupt service task is terminat- ed upon execution of an interrupt return instruction [reti]. interrupt acceptance 1. the interrupt master enable flag (i-flag) is cleared to 0 to temporarily disable the acceptance of any follow- ing maskable interrupts. when a non-maskable inter- rupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. interrupt request flag for the interrupt source accepted is cleared to 0. 3. the contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. the stack pointer decreases 3 times. 4. the entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. the instruction stored at the entry address of the inter- rupt service program is executed. ienh (interrupt enable high register) address : 0db h reset value : -0000000 b - kse bite int0e int1e t0e t1e int2e address : 0da h reset value : -0000--- b - reme ade sioe wte - - - ienl (interrupt enable low register) irqh (interrupt request high register) irql (interrupt request low register) 0 : disable 1 : enable enables or disables the interrupt individually if flag is cleared, the interrupt is disabled. 0 : not occurred 1 : interrupt request is occurred shows the interrupt occurrence bit : 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w bit : 7 6 5 4 3 2 1 0 r/w r/w r/w r/w address : 0dd h reset value : -0000000 b - ksif bitif int0if int1if t0if t1if int2if bit : 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w address : 0dc h reset value : -0000--- b - remif adif sioif wtif - - - bit : 7 6 5 4 3 2 1 0 r/w r/w r/w r/w
gms81c5108 june 2001 ver 1.0 67 figure 17-3 timing chart of interrupt acceptance and interrupt return instruction an interrupt request is not accepted until the i-flag is set to 1 even if a requested interrupt has higher priority than that of the current interrupt being serviced. when nested interrupt service is required, the i-flag should be set to 1 by ei instruction in the interrupt service program. in this case, acceptable interrupt sources are se- lectively enabled by the individual interrupt enable flags. saving/restoring general-purpose register during interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. if necessary, these registers should be saved by the software. also, when multiple interrupt ser- vices are nested, it is necessary to avoid using the same data memory area for saving registers. the following method is used to save/restore the general- purpose registers. example: register saving general-purpose registers are saved or restored by using push and pop instructions. v.l. system clock address bus pc sp sp-1 sp-2 v.h. new pc v.l. data bus not used pch pcl psw adl op code adh instruction fetch internal read internal write interrupt processing step interrupt service routine v.l. and v.h. are vector addresses. adl and adh are start addresses of interrupt service routine as vector contents. basic interval timer 012 h 0e3 h 0fffa h 0fffb h 0e h 2e h 0e312 h 0e313 h entry address correspondence between vector table address for bit interrupt and the entry address of the interrupt service program. vector table address intxx: push a push x push y ;save acc. ;save x reg. ;save y reg. interrupt processing pop y pop x pop a reti ;restore y reg. ;restore x reg. ;restore acc. ;return main routine interrupt service routine saving registers restoring registers acceptance of interrupt interrupt return
gms81c5108 68 june 2001 ver 1.0 17.2 brk interrupt software interrupt can be invoked by brk instruction, which has the lowest priority order. interrupt vector address of brk is shared with the vector of tcall 0 (refer to program memory section). when brk interrupt is generated, b-flag of psw is set to distin- guish brk from tcall 0. each processing step is determined by b-flag as shown in figure 17-4. figure 17-4 execution of brk/tcall0 17.3 multi interrupt if two requests of different priority levels are received si- multaneously, the request of higher priority level is ser- viced. if requests of the interrupt are received at the same time simultaneously, an internal polling sequence deter- mines by hardware which request is serviced. however, multiple processing through software for special features is possible. generally when an interrupt is accept- ed, the i-flag is cleared to disable any further interrupt. but as user sets i-flag in interrupt routine, some further inter- rupt can be serviced even if certain interrupt is in progress. example: even though timer1 interrupt is in progress, int0 interrupt serviced without any suspend. timer1: push a push x push y ldm ienh,#80h ; enable int0 only ldm ienl,#0 ; disable other ei ; enable interrupt : : : : : : ldm ienh,#0ffh ; enable all interrupts ldm ienl,#0f0h pop y pop x pop a reti . figure 17-5 execution of multi interrupt b-flag brk interrupt routine reti tcall0 routine ret brk or tcall0 =0 =1 enable int0 timer 1 service int0 service main program service occur timer1 interrupt occur int0 ei disable other enable int0 enable other in this example, the int0 interrupt can be serviced without any pending, even timer1 is in progress. because of re-setting the interrupt enable registers ienh,ienl and master enable "ei" in the timer1 routine.
gms81c5108 june 2001 ver 1.0 69 17.4 external interrupt the external interrupt on int0, int1 and int2 pins are edge triggered depending on the edge selection register iesr (address 0d8 h ) as shown in figure 17-6. the edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. figure 17-6 external interrupt block diagram example: to use as an int0 and int2 : : ; **** set port as an input port r0 ldm r0dr,#1111_1010b ; ; **** set port as an interrupt port ldm pmr,#0000_0101b ; ; **** set falling-edge detection ldm iesr,#0001_0001b : : : response time the int0, int1 and int2 edge are latched into int0f, int1f and int2f at every machine cycle. the values are not actually polled by the circuitry until the next machine cycle. if a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the re- quested service routine will be the next instruction to be executed. the div itself takes twelve cycles. thus, a max- imum of twelve complete machine cycles elapse between activation of an external interrupt request and the begin- ning of execution of the first instruction of the service rou- tine. interrupt response timings are shown in figure 17-7. figure 17-7 interrupt response timing diagram int0if int0 int0 interrupt int1if int1 int1 interrupt int2if int2 int2 interrupt iesr [0d8 h ] edge selection iesr (ext. interrupt edge selection register) address : 0d8 h reset value : --000000 b int21 int2[1:0] (int2 edge selections) bit : 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w int20 int10 int11 int01 int00 00 : int. disable 01 : falling (1-to-0 transition) 10 : rising (0-to-1 transition) 11 : both (rising & falling) int1[1:0] (int1 edge selection) 00 : int. disable 01 : falling (1-to-0 transition) 10 : rising (0-to-1 transition) 11 : both (rising & falling) int0[1:0] (int0 edge selections) 00 : int. disable 01 : falling (1-to-0 transition) 10 : rising (0-to-1 transition) 11 : both (rising & falling) - - interrupt edge selection register) interrupt goes active interrupt latched interrupt processing interrupt routine 8 f osc max. 12 f osc
gms81c5108 70 june 2001 ver 1.0 18. key scan the key-scan block consists of key scan mode register (ksmr) and r1 pull-up register (r1pu). when the key scan interrupt is used, key scan mode register ksmr (ad- dress 0f0 h ) should be set properly as shown in figure 18- 1. the pins which is to be used as key scan input should be set by ksmr and the strobe output pins should be set as open drain. the strobe output pins could be selected from among r0[7:0], r1[7:0], r2[3:0] and r3[3:0]. if the l signal is input to any one or more of key scan in- put pins, the ksif request flag is set to 1. this generates an interrupt request. it also can be used in the way of re- lease from stop mode. figure 18-1 key scan interrupt block diagram usage of key scan when key board scanning, it is recommended that set the output strobe to l first and then read r1 port after 60us delay time. because the rising time of the output strobe port from l to h is so long. the figure 18-2 explain this reason. figure 18-2 key scan timing r13/ks3 r12/ks2 r11/ks1 r10/ks0 r1pu[7:0] r17/ks7 r16/ks6 r15/ks5 r14/ks4 v dd ksmr ksif key scan interrupt ksmr (key scan mode register) address : 0f0 h reset value : 00 h bit : 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w ks7 ks6 ks5 ks4 ks3 ks2 ks1 ks0 0 : port function (i/o) selection 1 : key scan input selection 60 m s r3<0> r3<1> 60 m s r1 port read timing if the rising time is so long, the key scanning could be detected double key with r3<0> and r3<1>. ;program example, ldm call lda ;r3<0> port set to low ;60us time delay routine ;read r1 port r3,#0000_1110b r1 delay_60us
gms81c5108 june 2001 ver 1.0 71 19. lcd driver the gms81c5108 has the circuit that directly drives the liquid crystal display (lcd) and its control circuit. the segment/common driver directly drives the lcd panel, and the lcd controller generates the segment/common signals according to the ram which stores display data. in addition, vcl2 ~ vcl0 pin are provided as the drive pow- er pins. the gms81c5108 has the following pins connected with lcd. 1. segment output port 37 pins (seg0-seg36) 2.common output port 4 pins (com0-com3) 19.1 configuration of lcd driver figure 19-1 shows the configuration of the lcd driver. figure 19-1 lcd driver block diagram com0 seg34/com3 seg35/com2 seg36/com1 seg0 display data select control display data buffer register lcd display memory segment/common driver (37nibbles) ? 32 ? 64 ? 128 ? 256 timing control seg33 select clock clock lcr[0f1h] lcd lcden internal bus line mux wtmr[1:0] mux f sub f main 00 10 prescaler f main ? ? ? ? 2 7 01 select duty control register
gms81c5108 72 june 2001 ver 1.0 19.2 control of lcd driver circuit the lcd driver is controlled by the lcd control register (lcr). the lcr[1:0] determines the frequency of com signal scanning of each segment output. reset clears the lcd control register lcr values to logic zero. the lcd display can continue to operate during sleep and stop modes if a sub-frequency clock is used as system clock source. the constant voltage booster circuit for using lcd driver is built in, so the definite voltage could supplied re- gardless of power source voltage fluctuations. note: the sub clock is used as voltage booster source clock, so the stabilization time is need to use voltage boost- er. normally, the stabilization time is need more than 500ms. the external bias registers cannot be used for lcd display supply voltage. figure 19-2 lcd control register selecting frame frequency frame frequency is set to the base frequency as shown in the following table 19-1. the f s is selected to f sub (sub clock) which is 32.768khz. the matters to be attended to use lcd driver in reset state, lcd source clock is sub clock. so, when the power is supplied, the lcd display would be flickered be- fore the oscillation of sub clock is stabilized. it is recom- mended to use lcd display on after the stabilization time of sub clock is considered enough. if the lcd is reset dur- ing display, the display would be blotted by the capacity of lcd power circuit. the external circuit of constant voltage booster for using lcd driver is shown at right. figure 19-3 lcd power booster circuit lcden (lcd display enable bit) 0: lcd display disable 1: lcd display enable vbcl (voltage booster enable bit) 0: voltage booster disable 1: voltage booster enable lcdd[1:0] (lcd duty selection) 00: 1/4 duty 01: 1/3 duty (com[3] are used as seg[34]) lcr(lcd control register) address : 0f1 h reset value : --000000 b - - lcden vbcl lcdd1 lcdd0 lck1 lck0 bit : 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w lck (lcd clock source selection) 00: f s ? 32 01: f s ? 64 10: f s ? 128 11: f s ? 256 * the fs can be selected among f sub (sub clock), f main ? 2 7 (main clck) and f main (main clock). 10: 1/2 duty (com[3:2] are used as seg[34:35]) 11: static (com[3:1] are used as seg[34:36]) and sub or main is selected by wtck[1:0] of wtmr. lcr[1:0] lcd clock frame frequency (hz) duty = static duty = 1/2 duty = 1/3 duty = 1/4 00 01 10 11 f s ? 32 f s ? 64 f s ? 128 f s ? 256 1024 512 256 128 512 256 128 64 341.3 170.7 85.3 42.7 256 128 64 32 table 19-1 setting of lcd frame frequency vcl2 vcl1 vcl0 r1 r2 c1 gms81c5108 gms87c5108 c2 c3 c4 caph capl c1~c4=0.47uf r1=400k w r2=1m w
gms81c5108 june 2001 ver 1.0 73 19.3 lcd display memory display data are stored to the display data area (page 1) in the data memory. the display data stored to the display data area (address 0100 h -0124 h ) are read automatically and sent to the lcd driver by the hardware. the lcd driver generates the seg- ment signals and common signals in accordance with the display data and drive method. therefore, display patterns can be changed by only overwriting the contents of the dis- play data area with a program. the table look up instruc- tion is mainly used for this overwriting. figure 19.3 shows the correspondence between the display data area and the seg/com pins. the lcd lights when the display data is 1 and turn off when 0. lcd display memory in this location that are not used for lcd display can be allocated for general purpose use. the seg data for display is controlled by rpr (ram pag- ing register). figure 19-4 setting of ram paging register figure 19-5 lcd display memory rpr (ram paging register) address : 0f3 h reset value : ------00 b - bit : 7 6 5 4 3 2 1 0 r/w r/w r/w r/w - - rpr1 rpr0 - - rpr0 ram page instruction rpr1 x 0 page clrg x 0 0 page setg 0 1 1 page setg 0 - seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 com0 com1 com2 com3 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 01234567 bit 0100 h 0101 h 0102 h 0103 h 0104 h 0105 h 0106 h 0107 h 0108 h 0109 h 010a h 010b h 010c h 010d h 010e h 010f h 0110 h 0111 h 0112 h 0113 h 0114 h 0115 h 0116 h 0117 h 0118 h 0119 h 011a h 011b h 011c h 011d h 011e h 011f h 0120 h 0121 h 0122 h 0123 h 0124 h
gms81c5108 74 june 2001 ver 1.0 19.4 control method of lcd driver initial setting flow chart of initial setting is shown in figure 19-6. example: driving of lcd . figure 19-6 initial setting of lcd driver figure 19-7 example of connection com & seg display data normally, display data are kept permanently in the pro- gram memory and then stored at the display data area by the table look-up instruction. this can be explained using character display with 1/4 duty lcd as an example as well as any lcd panel. the com and seg connections to the lcd and display data are the same as those shown is fig- ure 19-7. following is showing the programming example for displaying character. note: when power on reset, sub oscillation start up time is required. enable lcd display after sub oscillation is sta- bilized, or lcd may occur flicker at power on time shortly. clear lcd display memory select frame frequency turn on lcd ldm lcr,#12h ;f f =64hz, 1/4 duty (f sub = 32.768khz) : ldm rpr,#1 ;select lcd memory(1 page) setg ldx #0 c_lcd1: lda #0 ;ram clear ;(0100h->0124h) sta {x}+ cmpx #025h bne c_lcd1 clrg : set1 lcr.5 ;enable display : setting of lcd drive method initialize of display memory enable display seg0 seg1 com3 com0 com1 com2 example: display 2 11 10 01 01 ** ** ** ** 100 h 101 h 31 20 bit 7 5 64 note: * are dont care.
gms81c5108 june 2001 ver 1.0 75 lcd waveform the lcd duty can be selected by lcr register. the kinds of lcd waveforms are four totally. among them, static and 1/4 duty waveforms are shown figure 19-8. figure 19-8 example of lcd drive output : clrg ldx # gms81c5108 76 june 2001 ver 1.0 20. remocon carrier generator the gms81c5108 has a circuit to generate carriers for the remote controller. this circuit consists of remocon mode register (rmr), carrier frequency high selection (cf- hs), carrier frequency low selection (cfls), remocon data high register (rdhr), remocon data low register (rdlr), remocon data counter (rdc), remocon output data register (rodr) and remocon output buffer (rob) as shown in figure 20-1. a carrier duty and fre- quency are determined by the contents of these registers. a source clock input to the 6-bit counter is selected by diving the frequency of the system clock by two (main or sub clock). 20.1 remocon signal output control the output of the remout pin which outputs carriers is controlled by rodr and rob register. while the bit-0 of rodr is 1, the remout pin outputs a carrier signal generated by the remote controller carrier generator. while this bit is 0, the output of the remout pin is low. the content of the rob is automatically transferred to the rodr by an interrupt signal generated by the 8-bit timer. the content of the rodr.0 is output to the remout pin. namely, the remout pin outputs a high-level signal when rodr.0 is 1 and a low-level signal when rodr.0 is 0. figure 20-1 remocon carrier generator block diagram scmr[1:0] 2 0x 1x x in sx in pre- scaler rdck[2:0] fxin ? 8 fxin ? 16 2 ren 1 1 1 1 0 & cck[1:0] remocon remf interrupt fxin ? 32 fxin ? 64 fxin ? 128 fxin ? 256 fxin ? 512 fxin ? 1 fxin ? 2 fxin ? 4 fxin ? 8 mux mux ren 1 1 1 1 0 6-bit counter cfhs (6-bit) cfls (6-bit) comparator rdc(8bit) rdhr (8-bit) rdlr (8-bit) comparator rdpe ren rob (1bit) rodr (1bit) remout rmr (remocon mode register) address : 0f6 h reset value : -0000000 b - ren cck1 cck0 rdpe rdck2 rdck1 rdck0 bit : 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w ren (remocon operation enable) 0 : disable rdck[2:0] (remocon data clock selection) cck[1:0] (carrier clock source selection) 1 : enable rdpe (remocon data pulse enable) 0 : disable 1 : enable 111: carrier signal fxin is f main or f sub. 000: f main ? 2 3 001: f main ? 2 4 010: f main ? 2 5 011: f main ? 2 6 100: f main ? 2 7 101: f main ? 2 8 110: f main ? 2 9 f main : main-clock frequency f sub : sub-clock frequency or f sub ? 2 4 or f sub ? 2 3 or f sub ? 2 6 or f sub ? 2 5 or f sub ? 2 7 or f sub ? 2 9 or f sub ? 2 8 00: f main 01: f main ? 2 10: f main ? 2 2 11: f main ? 2 3 or f sub ? 2 or f sub or f sub ? 2 3 or f sub ? 2 2
gms81c5108 june 2001 ver 1.0 77 figure 20-2 remocon registers 20.2 carrier frequency the carrier frequency and the pulse of data are calculated by below formula. the the lengths of carrier frequency and pulse of data are shown in figure 20-3. t h = source clock(rmr[5:4]) cfhs t l = source clock(rmr[5:4]) cfhs f c (carrier frequency) = 1/(t h +t l ) t dh = source clock(rmr[2:0]) rdhr t dl = source clock(rmr[2:0]) rdlr cfhs (carrier frequency high selection) address : 0f7 h - - cfh5 cfh4 cfh3 cfh2 cfh1 cfh0 bit : 7 6 5 4 3 2 1 0 wwww ww rdhr (remocon data high register) address : 0f9 h rdh7 rdh6 rdh5 rdh4 rdh3 rdh2 rdh1 rdh0 bit : 7 6 5 4 3 2 1 0 wwww ww w w reset value : --111111 b carrier high interval = the value of cfhs x clock source period cfls (carrier frequency low selection) address : 0f8 h - - cfl5 cfl4 cfl3 cfl2 cfl1 cfl0 bit : 7 6 5 4 3 2 1 0 wwww ww reset value : --111111 b carrier low interval = the value of cfls x clock source period reset value : 11111111 b remocon data high interval = the value of rdhr x clock source period rdlr (remocon data low register) address : 00fa h rdl7 rdl6 rdl5 rdl4 rdl3 rdl2 rdl1 rdl0 bit : 7 6 5 4 3 2 1 0 wwww ww w w reset value : 11111111 b remocon data low interval = the value of rdlr x clock source period rdc (remocon data counter) address : 00fa h rdc7 rdc6 rdc5 rdc4 rdc3 rdc2 rdc1 rdc0 bit : 7 6 5 4 3 2 1 0 rrrr rr r r reset value : 00000000 b remocon data counter value rodr (remocon output data register) address : 0fb h - - - - - - - rdd0 bit : 7 6 5 4 3 2 1 0 r/w reset value : -------0 b remocon data output value rob (remocon output buffer) address : 0fc h - - - - - - - rdb0 bit : 7 6 5 4 3 2 1 0 r/w reset value : -------0 b remocon data output buffer
gms81c5108 78 june 2001 ver 1.0 figure 20-3 carrier frequency & pulse of data the table 20-1 shows high and low length of carrier fre- quency according to cfls and cfhs. this only shows when the source clock is selected f main and f main ?2 2 at 4mhz. table 20-1 length of carrier frequency (at 4mhz) rod0 = 01 h rod0 = 00 h t dl t dh as soon as the carrier interrupt is occurred, the content of rob is transferred to rodr. t h t l carrier frequency pulse of data set value selection of ps0 selection of ps2 set value selection of ps0 selection of ps2 cfhs cfls t h (us) t l (us) t h (us) t l (us) cfhs cfls t h (us) t l (us) t h (us) t l (us) 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 10 h 11 h 12 h 13 h 14 h 15 h 16 h 17 h 18 h 19 h 1a h 1b h 1c h 1d h 1e h 1f h 00 h 01 h 02 h 03h 04 h 05 h 06 h 07 h 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 10 h 11 h 12 h 13 h 14 h 15 h 16 h 17 h 18 h 19 h 1a h 1b h 1c h 1d h 1e h 1f h - 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00 6.25 6.50 6.75 7.00 7.25 7.50 7.75 - 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00 6.25 6.50 6.75 7.00 7.25 7.50 7.75 - 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 11.00 12.00 13.00 14.00 15.00 16.00 17.00 18.00 19.00 20.00 21.00 22.00 23.00 24.00 25.00 26.00 27.00 28.00 29.00 30.00 31.00 - 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 11.00 12.00 13.00 14.00 15.00 16.00 17.00 18.00 19.00 20.00 21.00 22.00 23.00 24.00 25.00 26.00 27.00 28.00 29.00 30.00 31.00 20 h 21 h 22 h 23 h 24 h 25 h 26 h 27 h 28 h 29 h 2a h 2b h 2c h 2d h 2e h 2f h 30 h 31 h 32 h 33 h 34 h 35 h 36 h 37 h 38 h 39 h 3a h 3b h 3c h 3d h 3e h 3f h 20 h 21 h 22 h 23 h 24 h 25 h 26 h 27 h 28 h 29 h 2a h 2b h 2c h 2d h 2e h 2f h 30 h 31 h 32 h 33 h 34 h 35 h 36 h 37 h 38 h 39 h 3a h 3b h 3c h 3d h 3e h 3f h 8.00 8.25 8.50 8.75 9.00 9.25 9.50 9.75 10.00 10.25 10.50 10.75 11.00 11.25 11.50 11.75 12.00 12.25 12.50 12.75 13.00 13.25 13.50 13.75 14.00 14.25 14.50 14.75 15.00 15.25 15.50 15.75 8.00 8.25 8.50 8.75 9.00 9.25 9.50 9.75 10.00 10.25 10.50 10.75 11.00 11.25 11.50 11.75 12.00 12.25 12.50 12.75 13.00 13.25 13.50 13.75 14.00 14.25 14.50 14.75 15.00 15.25 15.50 15.75 32.00 33.00 34.00 35.00 36.00 37.00 38.00 39.00 40.00 41.00 42.00 43.00 44.00 45.00 46.00 47.00 48.00 49.00 50.00 51.00 52.00 53.00 54.00 55.00 56.00 57.00 58.00 59.00 60.00 61.00 62.00 63.00 32.00 33.00 34.00 35.00 36.00 37.00 38.00 39.00 40.00 41.00 42.00 43.00 44.00 45.00 46.00 47.00 48.00 49.00 50.00 51.00 52.00 53.00 54.00 55.00 56.00 57.00 58.00 59.00 60.00 61.00 62.00 63.00
gms81c5108 june 2001 ver 1.0 79 example: carrier frequency = 37.8khz, high = 8.52ms, low = 4.24ms, @4mhz rem_sig: ldm rmr,#0001_0010b ;carrier clock(ps1), remocon data clock(ps5) ldm cfhs,#18 ;carrier low(ir led)=18*ps1(0.5us)=9us ldm cfls,#35 ;carrier high(ir led)=35*ps1(0.5us)=17.5us clr1 rod0 ldm r_bit,#1111_1000b ldm rdhr,#213 ;213*5*ps5(8us)=8.52ms ldm rdlr,#177 ;177*3*ps5(8us)=4.248ms ldx #9 call data set1 rmr.6 ;remocon operation enable set1 rmr.3 ;remocon data pulse enable set1 ienl.6 ;remocon int. loop1: nop cmpx #0 bne loop1 finish: clr1 rod0 clr1 rob0 ret ;******** data: rol r_bit bcs set_rob0 clr1 rob0 ret set_rob0:set1rob0 ret ;***********************************************; ; remocon int service routine ; ;***********************************************; ; remocon_int: call data dec x reti
gms81c5108 80 june 2001 ver 1.0 21. oscillator circuit the gms81c5108 has two oscillation circuits internally. x in and x out are input and output for main frequency and sx in and sx out are input and output for sub frequency, respectively, inverting amplifier which can be configured for being used as an on-chip oscillator, as shown in figure 21-1. figure 21-1 oscillation circuit oscillation circuit is designed to be used either with a ce- ramic resonator or crystal oscillator. since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. in addition, see figure 21-2 for the layout of the crystal. note: minimize the wiring length. do not allow the wiring to intersect with other signal conductors. do not allow the wir- ing to come near changing high current. set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground it to any ground pattern where high cur- rent is present. do not fetch signals from the oscillator. figure 21-2 layout of oscillator pcb circuit x out x in v ss recommend c1,c2 = 20pf c1 c2 x out x in external clock open x out x in external oscillator rc oscillator crystal or ceramic oscillator sx out sx in v ss recommend c3,c4 = 30pf c3 c4 32.768khz 4.19mhz crystal oscillator ceramic resonator c1,c2 = 20pf select r value according to ac characteristics. r ext the cap. is built in(5pf). x out x in
gms81c5108 june 2001 ver 1.0 81 22. reset the gms81c5108 have two types of reset generation pro- cedures; one is an external reset input, the other is a watch- dog timer reset. table 22-1 shows on-chip hardware ini- tialization by reset action. table 22-1 initializing internal status by reset action 22.1 external reset input the reset input is the reset pin, which is the input to a schmitt trigger. a reset in accomplished by holding the reset pin to low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is ap- plied, and the internal state is initialized. after reset, 65.5ms (at 4mhz) add with 7 oscillator periods are re- quired to start execution as shown in figure 22-2. internal ram is not affected by reset. when v dd is turned on, the ram content is indeterminate. therefore, this ram should be initialized before read or tested it. when the reset pin input goes to high, the reset opera- tion is released and the program execution starts at the vec- tor address stored at fffe h - ffff h . a connection for simple power-on-reset is shown in figure 22-1. figure 22-1 simple power-on-reset circuit figure 22-2 timing diagram after reset 22.2 watchdog timer reset refer to 13.2 watch dog timer on page 57. on-chip hardware initial value on-chip hardware initial value program counter (pc) (ffff h ) - (fffe h ) peripheral clock on ram page register (rpr) 0 svd enable g-flag (g) 0 control registers refer to table 8-1 on page 25 operation mode main-frequency clock voltage booster disable reset + - v dd v dd gnd mask option mcu 100k w 1uf main program system clock ? ? fffe ffff stabilization time t st = 65.5ms at 4mhz reset address data 1 2 3 4 5 6 7 ?? start ? ? ? fe ? adl adh op bus bus reset process step ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t st = x 256 f main ? 1024 1
gms81c5108 82 june 2001 ver 1.0 23. supply voltage detection the gms81c5108 has an on-chip low voltage detection circuitry to detect the v dd voltage. a configuration regis- ter, scmr, can enable or disable the low voltage detect circuitry. this gms81c5108 has two level detec- tor(svd0, svd1). the svd0 flag is set when the v dd falls below 2.2v and if the v dd is rise above 2.2v the svd0 is cleared automatically. the svd1 flag is set when the v dd falls below 1.7v and if this flag is set once, it is not cleared automatically although the v dd rises above 1.7v. it can be cleared by writing. if the svd1 is set, the mcu can be reset or frozen by the flag svrt. in the in-circuit emulator, supply voltage detection is not implemented and user can not experiment with it. therefore, after final development of user program, this function may be experimented or evaluated. figure 23-1 low voltage detector register figure 23-2 power fail processor situations * the values of 1.7v and 2.2v could be changed by 0.2v according to the process of work. r/w r/w r/w r/w sycc[1:0] (system clock control) 00: main clock on 01: main clock on 10: sub clock on (main clock on) 11: sub clock on (main clock off) scs[1:0] (system clock source select) initial value: 00 h address: 0f5 h scmr (system msb lsb r/w r/w r/w r svd[1:0] (svd flag) svd0 : set at vdd=2.2v svd1 : set at vdd=1.7v svrt (system reset control by svd1 bit) 0 : system reset by svd1 flag 1 : dont system reset by svd1 flag (freeze) sven (svd operation enable bit) 0 : svd operation enable 1 : svd operation disable clock mode register) f main ? 2 4 f main ? 2 3 f main ? 2 f main ? 2 6 or f sub ? 2 or f sub ? 2 3 or f sub ? 2 6 or f sub ? 2 4 internal reset internal reset internal reset v dd v dd v dd svd max svd min svd max svd min svd max svd min 65.5ms 65.5ms t < 65.5ms 65.5ms when svrt = 0 v dd v dd svd max svd min svd max svd min when svrt = 1 system clock system clock
gms81c5108 june 2001 ver 1.0 83 24. devemopment tools 24.1 otp programming the gms87c5108 is an otp (one time programmable) micro- controllers. its internal user memory is constructed with eprom (electrically programmable read only memory). the otp microcontroller is generally used for chip evaluation, first production, small amount production, fast mass production, etc. blank otps internal eprom is filled by 00 h , not ff h . note: in any case, you have to use the *.otp file for pro- gramming, not the *.hex file. after assemble, both otp and hex file are generated by automatically. the hex file is used during program emulation on the emulator. how to program to program the otp devices, user can use hynix own program- mer. hynix own programmer list manufacturer: hynix semiconductor programmer: choice-sigma choice-gang4 the choice-sigma is a hynix universal single programmer for all of hynix otp devices, also the choice-gang4 can program four otps at once for hynix otp. ask to hynix sales part for purchasing or more detail programming procedure 1. select device gms87c5108 you want. 2. load the *.otp file from the pc. the file is composed of motorola-s1 format. 3. set the programming address range as below table. 4. mount the socket adapter on the programmer. 5. start program/verify. pin function v pp (program voltage) v pp is the input for the program voltage for programming the eprom. ce (chip enable) ce is the input for programming and verifying internal eprom. oe (output enable) oe is the input of data output control signal for verify. a0~a15 (address bus) a0~a15 are address input pins for internal eprom. o0~o7 (eprom data bus) these are data bus for internal eprom. address set value buffer start address e000 h buffer end address ffff h device start address e000 h
gms81c5108 84 june 2001 ver 1.0 24.2 emulator s/w setting power run stop sleep choice-dr. eva 81c51 b/d rev 1.0 s/n. --------------- connecta connectb connectc j_userb reset j_usera v_user x1 (osc) x2 /reset xout lcd_vdd vlcdc seg46 seg44 seg42 seg40 seg38 vreg com1/s36 com3/s34 seg32 seg30 seg28 seg26 seg24 seg22 seg20 seg18 seg16 seg14 seg12 seg10 seg8 seg6 seg4 seg2 seg0 seg47 seg45 seg43 seg41 seg39 seg37 com0 com2/s35 seg33 seg31 seg29 seg27 seg25 seg23 seg21 seg19 seg17 seg15 seg13 seg11 seg9 seg7 seg5 seg3 seg1 gnd vcl1 vlcdc cb gnd remout (toned) gnd r36 r34 r21 r23 r25 r27 r16 r14 r12 r10 r06 r04 r02 r00 r32 r30 +5v gnd vcl0 vcl2 ca gnd /u_rst u_xout gnd r37 r35 r20 r22 r24 r26 r17 r15 r13 r11 r07 r05 r03 r01 r33 r31 +5v j_userb j_usera sw 4 sw 5 external oscillator socket gms81c51 eva +5v sw 2 2 1 off on off on sw 1 vr1 vr2 1 2 3 4 5 6 7 1 2
gms81c5108 june 2001 ver 1.0 85 dip switch and vr setting before execute the user program, keep in your mind the below configuration dip s/w, vr description on/off setting sw1 - emulator reset switch. reset the emulator. reset the emulator. sw2 1 normally off . eva. chip can be reset by external user target system board. on : reset is available by user target system board. off : mcu is reset by rest switch on eva. board. 2 normally off . mcu xout pin are disconnected by emulator internally. some cir- cumstance user may connect this circuit. on : output xout signal off : disconnect circuit sw4 1 2 3 normally on . it serves the external bias resistors. if user want to use external circuit instead of internal r, turn on these switches. 4 5 6 lcd voltage booster circuit. must be on position. it is used for the gms81c5108. 7 select the stack page. must be off position. this switch decide the stack page 0 (off) or page 1 (on). on : for the gms81c7xxx off : for the gms81c5108 8 gms81c5108 detect the v dd voltage but emulator can not do because emulator can not operate if v dd is below normal opr. voltage (5v), this switch serves lvd environment through the applying 0v to lvd pin of eva. chip during 5v normal operation. position on during normal opera- tion. on : normal operation off : force to detect the lvd, refer to "23. supply voltage detec- tion" on page 82. sw2-1 reset pin eva. chip sw2-2 xout pin eva. chip oscillator vcl1 vcl2 external resistor vcl0 v ss v dd adjust contrast sw4-1 sw4-2 sw4-3 0.47uf 3 10k w 3 and capacitor vr1 50k w sw4-8 v dd eva. chip lvd pin off on off on
gms81c5108 86 june 2001 ver 1.0 sw5 1 internal power supply to sub-oscillation circuit. must be on position. 2 reserved for other purpose. must be off position. vr1 - adjust the lcd contrast. it control the vcl2 voltage. refer to above sw4-1,2,3 figure. adjust the proper position as well as lcd display good. vr2 - reserved for other purpose. dont care. dip s/w, vr description on/off setting off on
gms81c5108 june 2001 ver 1.0 87 book history this book ver 1.0 (june 2001) first edition.
appendix
gms81c5108 appendix june 2001 ver 1.0 i a. control register list address register name symbol r/w initial value page 76543210 00c0 r0 port data register r0 r/w 0 0 0 0 0 0 0 0 32 00c1 r1 port data register r1 r/w 0 0 0 0 0 0 0 0 32 00c2 r2 port data register r2 r/w - - - - 0 0 0 0 33 00c3 r3 port data register r3 r/w - - - - 0 0 0 0 33 00c8 r0 port i/o direction register r0dr w 0 0 0 0 0 0 0 0 32 00c9 r1 port i/o direction register r1dr w 0 0 0 0 0 0 0 0 32 00ca r2 port i/o direction register r2dr w - - - - 0 0 0 0 33 00cb r3 port i/o direction register r3dr w - - - - 0 0 0 0 33 00d0 r0 port pull-up register r0pu w 0 0 0 0 0 0 0 0 32 00d1 r1 port pull-up register r1pu w 0 0 0 0 0 0 0 0 32 00d2 r2 port pull-up register r2pu w - - - - 0 0 0 0 33 00d3 r3 port pull-up register r3pu w - - - - 0 0 0 0 33 00d4 r0 port open drain control register r0cr w 0 0 0 0 0 0 0 0 32 00d5 r1 port open drain control register r1cr w 0 0 0 0 0 0 0 0 32 00d6 r2 port open drain control register r2cr w - - - - 0 0 0 0 33 00d7 r3 port open drain control register r3cr w - - - - 0 0 0 0 33 00d8 ext. interrupt edge selection register iesr r/w - - 000000 69 00d9 port selection register pmr r/w - 0 - 0 0 0 0 0 32 00da interrupt enable low register ienl r/w - 0 0 0 0 - - - 65 00db interrupt enable high register ienh r/w - 0 0 0 0 0 0 0 65 00dc interrupt request flag low register irql r/w - 0 0 0 0 - - - 65 00dd interrupt request flag high register irqh r/w - 0 0 0 0 0 0 0 65 00de sleep mode register smr r/w - - - - - - - 0 39 00e0 timer 0 mode register tm0 r/w - - 0 0 0 0 0 0 45 00e1 timer 0 counter register t0 r 0 0 0 0 0 0 0 0 45 timer 0 data register tdr0 w 1 1 1 1 1 1 1 1 45 timer 0 input capture register cdr0 r 0 0 0 0 0 0 0 0 45 00e2 timer 1 mode register tm1 r/w 00000000 45 00e3 timer 1 data register tdr1 w 1 1 1 1 1 1 1 1 45 pwm0 pulse period register t1ppr w 1 1 1 1 1 1 1 1 45 00e4 timer 1 counter register t1 r 0 0 0 0 0 0 0 0 45 timer 1 input capture register cdr1 r 0 0 0 0 0 0 0 0 45 pwm0 pulse duty register t1pdr r/w 00000000 45 00e5 pwm0 high register pwmhr w - - - - 0 0 0 0 45 00ec a/d converter mode register admr r/w - 0 - - 0 0 0 1 58 00ed a/d converter data register addr r x x x x x x x x 58
gms81c5108 appendix ii june 2001 ver 1.0 00ef watch timer mode register wtmr r/w - 0 0 0 0 0 0 0 56 00f0 key scan mode register ksmr r/w 0 0 0 0 0 0 0 0 70 00f1 lcd control register lcr r/w 0 0 0 0 0 0 0 0 72 00f3 ram paging register rpr r/w - - - - - - 0 0 73 00f4 basic interval timer register bitr r 0 0 0 0 0 0 0 0 43 clock control register ckctlr w - - - - 0 1 1 1 43 00f5 system clock mode register scmr r/w 0 0 0 0 0 0 0 0 34 00f6 remocon mode register rmr r/w - 0 0 0 0 0 0 0 76 00f7 carrier frequency high selection cfhs w - - 1 1 1 1 1 1 76 00f8 carrier frequency low selection cfls w - - 1 1 1 1 1 1 76 00f9 remocon data high register rdhr w 1 1 1 1 1 1 1 1 76 00fa remocon data low register rdlr w 1 1 1 1 1 1 1 1 76 remocon data counter rdc r 0 0 0 0 0 0 0 0 76 00fb remocon output data register rodr r/w - - - - - - - 0 76 00fc remocon output buffer rob r/w - - - - - - - 0 76 00fd buzzer data register bdr w 0 0 0 0 0 0 0 0 60 00fe serial i/o mode register siom r/w 0 0 0 0 0 0 0 1 62 00ff serial i/o data register siod r/w x x x x x x x x 62 address register name symbol r/w initial value page 76543210
gms81c5108 appendix june 2001 ver 1.0 iii b. instruction b.1 terminology list terminology description a accumulator x x - register y y - register psw program status word #imm 8-bit immediate data dp direct page offset address !abs absolute address [ ] indirect expression { } register indirect expression { }+ register indirect expression, after that, register auto-increment .bit bit position a.bit bit position of accumulator dp.bit bit position of direct page memory m.bit bit position of memory data (000 h ~0fff h ) rel relative addressing data upage u-page (0ff00 h ~0ffff h ) offset address n table call number (0~15) + addition x upper nibble expression in opcode y upper nibble expression in opcode - subtraction multiplication / division ( ) contents expression and or ? exclusive or ~not ? assignment / transfer / shift left ? shift right ? exchange = equal 1 not equal 0 bit position 1 bit position
gms81c5108 appendix iv june 2001 ver 1.0 b.2 instruction map low high 00000 00 00001 01 00010 02 00011 03 00100 04 00101 05 00110 06 00111 07 01000 08 01001 09 01010 0a 01011 0b 01100 0c 01101 0d 01110 0e 01111 0f 000 - set1 dp.bit bbs a.bit,rel bbs dp.bit,rel adc #imm adc dp adc dp+x adc !abs asl a asl dp tcall 0 seta1 .bit bit dp pop a push a brk 001 clrc sbc #imm sbc dp sbc dp+x sbc !abs rol a rol dp tcall 2 clra1 .bit com dp pop x push x bra rel 010 clrg cmp #imm cmp dp cmp dp+x cmp !abs lsr a lsr dp tcall 4 not1 m.bit tst dp pop y push y pcall upage 011 di or #imm or dp or dp+x or !abs ror a ror dp tcall 6 or1 or1b cmpx dp pop psw push psw ret 100 clrv and #imm and dp and dp+x and !abs inc a inc dp tcall 8 and1 and1b cmpy dp cbne dp+x txsp inc x 101 setc eor #imm eor dp eor dp+x eor !abs dec a dec dp tcall 10 eor1 eor1b dbne dp xma dp+x tspx dec x 110 setg lda #imm lda dp lda dp+x lda !abs txa ldy dp tcall 12 ldc ldcb ldx dp ldx dp+y xcn das 111 ei ldm dp,#imm sta dp sta dp+x sta !abs tax sty dp tcall 14 stc m.bit stx dp stx dp+y xax stop low high 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1a 11011 1b 11100 1c 11101 1d 11110 1e 11111 1f 000 bpl rel clr1 dp.bit bbc a.bit,rel bbc dp.bit,rel adc {x} adc !abs+y adc [dp+x] adc [dp]+y asl !abs asl dp+x tcall 1 jmp !abs bit !abs addw dp ldx #imm jmp [!abs] 001 bvc rel sbc {x} sbc !abs+y sbc [dp+x] sbc [dp]+y rol !abs rol dp+x tcall 3 call !abs test !abs subw dp ldy #imm jmp [dp] 010 bcc rel cmp {x} cmp !abs+y cmp [dp+x] cmp [dp]+y lsr !abs lsr dp+x tcall 5 mul tclr1 !abs cmpw dp cmpx #imm call [dp] 011 bne rel or {x} or !abs+y or [dp+x] or [dp]+y ror !abs ror dp+x tcall 7 dbne y cmpx !abs ldya dp cmpy #imm reti 100 bmi rel and {x} and !abs+y and [dp+x] and [dp]+y inc !abs inc dp+x tcall 9 div cmpy !abs incw dp inc y tay 101 bvs rel eor {x} eor !abs+y eor [dp+x] eor [dp]+y dec !abs dec dp+x tcall 11 xma {x} xma dp decw dp dec y tya 110 bcs rel lda {x} lda !abs+y lda [dp+x] lda [dp]+y ldy !abs ldy dp+x tcall 13 lda {x}+ ldx !abs stya dp xay daa 111 beq rel sta {x} sta !abs+y sta [dp+x] sta [dp]+y sty !abs sty dp+x tcall 15 sta {x}+ stx !abs cbne dp xyx nop
gms81c5108 appendix june 2001 ver 1.0 v b.3 instruction set arithmetic / logic operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. 2 adc dp 05 2 3 a ? ( a ) + ( m ) + c 3adc dp + x 06 2 4 4 adc !abs 07 3 4 nv--h-zc 5 adc !abs + y 15 3 5 6 adc [ dp + x ] 16 2 6 7 adc [ dp ] + y 17 2 6 8adc { x } 14 1 3 9 and #imm 84 2 2 logical and 10 and dp 85 2 3 a ? ( a ) ( m ) 11 and dp + x 86 2 4 12 and !abs 87 3 4 n-----z- 13 and !abs + y 95 3 5 14 and [ dp + x ] 96 2 6 15 and [ dp ] + y 97 2 6 16 and { x } 94 1 3 17 asl a 08 1 2 arithmetic shift left 18 asl dp 09 2 4 n-----zc 19 asl dp + x 19 2 5 20 asl !abs 18 3 5 21 cmp #imm 44 2 2 compare accumulator contents with memory contents ( a ) - ( m ) 22 cmp dp 45 2 3 23 cmp dp + x 46 2 4 24 cmp !abs 47 3 4 n-----zc 25 cmp !abs + y 55 3 5 26 cmp [ dp + x ] 56 2 6 27 cmp [ dp ] + y 57 2 6 28 cmp { x } 54 1 3 29 cmpx #imm 5e 2 2 compare x contents with memory contents 30 cmpx dp 6c 2 3 ( x ) - ( m ) n-----zc 31 cmpx !abs 7c 3 4 32 cmpy #imm 7e 2 2 compare y contents with memory contents 33 cmpy dp 8c 2 3 ( y ) - ( m ) n-----zc 34 cmpy !abs 9c 3 4 35 com dp 2c 2 4 1s complement : ( dp ) ? ~( dp ) n-----z- 36 daa df 1 3 decimal adjust for addition n-----zc 37 das cf 1 3 decimal adjust for subtraction n-----zc 38 dec a a8 1 2 decrement n-----z- 39 dec dp a9 2 4 m ? ( m ) - 1 n-----z- 40 dec dp + x b9 2 5 n-----z- 41 dec !abs b8 3 5 n-----z- 42 dec x af 1 2 n-----z- 43 dec y be 1 2 n-----z- ? ? ? ? ? ? ? ? 76543210 ? 0 ? c
gms81c5108 appendix vi june 2001 ver 1.0 44 div 9b 1 12 divide : ya / x q: a, r: y nv--h-z- 45 eor #imm a4 2 2 exclusive or 46 eor dp a5 2 3 a ? ( a ) ? ( m ) 47 eor dp + x a6 2 4 48 eor !abs a7 3 4 n-----z- 49 eor !abs + y b5 3 5 50 eor [ dp + x ] b6 2 6 51 eor [ dp ] + y b7 2 6 52 eor { x } b4 1 3 53 inc a 88 1 2 increment n-----zc 54 inc dp 89 2 4 m ? ( m ) + 1 n-----z- 55 inc dp + x 99 2 5 n-----z- 56 inc !abs 98 3 5 n-----z- 57 inc x 8f 1 2 n-----z- 58 inc y 9e 1 2 n-----z- 59 lsr a 48 1 2 logical shift right 60 lsr dp 49 2 4 n-----zc 61 lsr dp + x 59 2 5 62 lsr !abs 58 3 5 63 mul 5b 1 9 multiply : ya ? y a n-----z- 64 or #imm 64 2 2 logical or 65 or dp 65 2 3 a ? ( a ) ( m ) 66 or dp + x 66 2 4 67 or !abs 67 3 4 n-----z- 68 or !abs + y 75 3 5 69 or [ dp + x ] 76 2 6 70 or [ dp ] + y 77 2 6 71 or { x } 74 1 3 72 rol a 28 1 2 rotate left through carry 73 rol dp 29 2 4 n-----zc 74 rol dp + x 39 2 5 75 rol !abs 38 3 5 76 ror a 68 1 2 rotate right through carry 77 ror dp 69 2 4 n-----zc 78 ror dp + x 79 2 5 79 ror !abs 78 3 5 80 sbc #imm 24 2 2 subtract with carry 81 sbc dp 25 2 3 a ? ( a ) - ( m ) - ~( c ) 82 sbc dp + x 26 2 4 83 sbc !abs 27 3 4 nv--hzc 84 sbc !abs + y 35 3 5 85 sbc [ dp + x ] 36 2 6 86 sbc [ dp ] + y 37 2 6 87 sbc { x } 34 1 3 88 tst dp 4c 2 3 test memory contents for negative or zero, ( dp ) - 00 h n-----z- 89 xcn ce 1 5 exchange nibbles within the accumulator a 7 ~a 4 ? a 3 ~a 0 n-----z- no. mnemonic op code byte no cycle no operation flag nvgbhizc ? ? ? ? ? ? ? ? 76543210 0 ?? c ? ? ? ? ? ? ? ? 76543210 c ? ? ? ? ? ? ? ? 76543210 c
gms81c5108 appendix june 2001 ver 1.0 vii register / memory operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 lda #imm c4 2 2 load accumulator 2 lda dp c5 2 3 a ? ( m ) 3lda dp + x c6 2 4 4 lda !abs c7 3 4 5 lda !abs + y d5 3 5 n-----z- 6 lda [ dp + x ] d6 2 6 7 lda [ dp ] + y d7 2 6 8lda { x } d4 1 3 9 lda { x }+ db 1 4 x- register auto-increment : a ? ( m ) , x ? x + 1 10 ldm dp,#imm e4 3 5 load memory with immediate data : ( m ) ? imm -------- 11 ldx #imm 1e 2 2 load x-register 12 ldx dp cc 2 3 x ? ( m ) n-----z- 13 ldx dp + y cd 2 4 14 ldx !abs dc 3 4 15 ldy #imm 3e 2 2 load y-register 16 ldy dp c9 2 3 y ? ( m ) n-----z- 17 ldy dp + x d9 2 4 18 ldy !abs d8 3 4 19 sta dp e5 2 4 store accumulator contents in memory 20 sta dp + x e6 2 5 ( m ) ? a 21 sta !abs e7 3 5 22 sta !abs + y f5 3 6 -------- 23 sta [ dp + x ] f6 2 7 24 sta [ dp ] + y f7 2 7 25 sta { x } f4 1 4 26 sta { x }+ fb 1 4 x- register auto-increment : ( m ) ? a, x ? x + 1 27 stx dp ec 2 4 store x-register contents in memory 28 stx dp + y ed 2 5 ( m ) ? x -------- 29 stx !abs fc 3 5 30 sty dp e9 2 4 store y-register contents in memory 31 sty dp + x f9 2 5 ( m ) ? y -------- 32 sty !abs f8 3 5 33 tax e8 1 2 transfer accumulator contents to x-register : x ? a n-----z- 34 tay 9f 1 2 transfer accumulator contents to y-register : y ? a n-----z- 35 tspx ae 1 2 transfer stack-pointer contents to x-register : x ? sp n-----z- 36 txa c8 1 2 transfer x-register contents to accumulator: a ? x n-----z- 37 txsp 8e 1 2 transfer x-register contents to stack-pointer: sp ? x n-----z- 38 tya bf 1 2 transfer y-register contents to accumulator: a ? y n-----z- 39 xax ee 1 4 exchange x-register contents with accumulator :x ? a -------- 40 xay de 1 4 exchange y-register contents with accumulator :y ? a -------- 41 xma dp bc 2 5 exchange memory contents with accumulator 42 xma dp+x ad 2 6 ( m ) ? a n-----z- 43 xma {x} bb 1 5 44 xyx fe 1 4 exchange x-register contents with y-register : x ? y --------
gms81c5108 appendix viii june 2001 ver 1.0 16-bit operation bit manipulation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 addw dp 1d 2 5 16-bits add without carry ya ? ( ya ) + ( dp +1 ) ( dp ) nv--h-zc 2 cmpw dp 5d 2 4 compare ya contents with memory pair contents : (ya) - (dp+1)(dp) n-----zc 3decw dp bd 2 6 decrement memory pair ( dp+1)( dp) ? ( dp+1) ( dp) - 1 n-----z- 4 incw dp 9d 2 6 increment memory pair ( dp+1) ( dp) ? ( dp+1) ( dp ) + 1 n-----z- 5 ldya dp 7d 2 5 load ya ya ? ( dp +1 ) ( dp ) n-----z- 6 stya dp dd 2 5 store ya ( dp +1 ) ( dp ) ? ya -------- 7 subw dp 3d 2 5 16-bits subtract without carry ya ? ( ya ) - ( dp +1) ( dp) nv--h-zc no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 and1 m.bit 8b 3 4 bit and c-flag : c ? ( c ) ( m .bit ) -------c 2 and1b m.bit 8b 3 4 bit and c-flag and not : c ? ( c ) ~( m .bit ) -------c 3 bit dp 0c 2 4 bit test a with memory : mm----z- 4 bit !abs 1c 3 5 z ? ( a ) ( m ) , n ? ( m 7 ) , v ? ( m 6 ) 5 clr1 dp.bit y1 2 4 clear bit : ( m.bit ) ? 0 -------- 6 clra1 a.bit 2b 2 2 clear a bit : ( a.bit ) ? 0 -------- 7 clrc 20 1 2 clear c-flag : c ? 0 -------0 8 clrg 40 1 2 clear g-flag : g ? 0 --0----- 9 clrv 80 1 2 clear v-flag : v ? 0 -0--0--- 10 eor1 m.bit ab 3 5 bit exclusive-or c-flag : c ? ( c ) ? ( m .bit ) -------c 11 eor1b m.bit ab 3 5 bit exclusive-or c-flag and not : c ? ( c ) ? ~(m .bit) -------c 12 ldc m.bit cb 3 4 load c-flag : c ? ( m .bit ) -------c 13 ldcb m.bit cb 3 4 load c-flag with not : c ? ~( m .bit ) -------c 14 not1 m.bit 4b 3 5 bit complement : ( m .bit ) ? ~( m .bit ) -------- 15 or1 m.bit 6b 3 5 bit or c-flag : c ? ( c ) ( m .bit ) -------c 16 or1b m.bit 6b 3 5 bit or c-flag and not : c ? ( c ) ~( m .bit ) -------c 17 set1 dp.bit x1 2 4 set bit : ( m.bit ) ? 1 -------- 18 seta1 a.bit 0b 2 2 set a bit : ( a.bit ) ? 1 -------- 19 setc a0 1 2 set c-flag : c ? 1 -------1 20 setg c0 1 2 set g-flag : g ? 1 --1----- 21 stc m.bit eb 3 6 store c-flag : ( m .bit ) ? c -------- 22 tclr1 !abs 5c 3 6 test and clear bits with a : a - ( m ) , ( m ) ? ( m ) ~( a ) n-----z- 23 tset1 !abs 3c 3 6 test and set bits with a : a - ( m ) , ( m ) ? ( m ) ( a ) n-----z-
gms81c5108 appendix june 2001 ver 1.0 ix branch / jump operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 bbc a.bit,rel y2 2 4/6 branch if bit clear : -------- 2 bbc dp.bit,rel y3 3 5/7 if ( bit ) = 0 , then pc ? ( pc ) + rel 3 bbs a.bit,rel x2 2 4/6 branch if bit set : -------- 4 bbs dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ? ( pc ) + rel 5bcc rel 50 2 2/4 branch if carry bit clear if ( c ) = 0 , then pc ? ( pc ) + rel -------- 6bcs rel d0 2 2/4 branch if carry bit set if ( c ) = 1 , then pc ? ( pc ) + rel -------- 7beq rel f0 2 2/4 branch if equal if ( z ) = 1 , then pc ? ( pc ) + rel -------- 8bmi rel 90 2 2/4 branch if minus if ( n ) = 1 , then pc ? ( pc ) + rel -------- 9bne rel 70 2 2/4 branch if not equal if ( z ) = 0 , then pc ? ( pc ) + rel -------- 10 bpl rel 10 2 2/4 branch if minus if ( n ) = 0 , then pc ? ( pc ) + rel -------- 11 bra rel 2f 2 4 branch always pc ? ( pc ) + rel -------- 12 bvc rel 30 2 2/4 branch if overflow bit clear if (v) = 0 , then pc ? ( pc) + rel -------- 13 bvs rel b0 2 2/4 branch if overflow bit set if (v) = 1 , then pc ? ( pc ) + rel -------- 14 call !abs 3b 3 8 subroutine call 15 call [dp] 5f 2 8 m( sp) ? ( pc h ), sp ? sp - 1, m(sp) ? (pc l ), sp ? sp - 1, if !abs, pc ? abs ; if [dp], pc l ? ( dp ), pc h ? ( dp+1 ) . -------- 16 cbne dp,rel fd 3 5/7 compare and branch if not equal : -------- 17 cbne dp+x,rel 8d 3 6/8 if ( a ) 1 ( m ) , then pc ? ( pc ) + rel. 18 dbne dp,rel ac 3 5/7 decrement and branch if not equal : -------- 19 dbne y,rel 7b 2 4/6 if ( m ) 1 0 , then pc ? ( pc ) + rel. 20 jmp !abs 1b 3 3 unconditional jump 21 jmp [!abs] 1f 3 5 pc ? jump address -------- 22 jmp [dp] 3f 2 4 23 pcall upage 4f 2 6 u-page call m(sp) ? ( pc h ), sp ? sp - 1, m(sp) ? ( pc l ), sp ? sp - 1, pc l ? ( upage ), pc h ? 0ff h . -------- 24 tcall n na 1 8 table call : (sp) ? ( pc h ), sp ? sp - 1, m(sp) ? ( pc l ),sp ? sp - 1, pc l ? (table vector l), pc h ? (table vector h) --------
gms81c5108 appendix x june 2001 ver 1.0 control operation & etc. no. mnemonic op code byte no cycle no operation flag nvgbhizc 1brk 0f 1 8 software interrupt : b ? 1, m(sp) ? (pc h ), sp ? sp-1, m(s) ? (pc l ), sp ? sp - 1, m(sp) ? (psw), sp ? sp -1, pc l ? ( 0ffde h ) , pc h ? ( 0ffdf h ) . ---1-0-- 2 di 60 1 3 disable all interrupts : i ? 0 -----0-- 3 ei e0 1 3 enable all interrupt : i ? 1 -----1-- 4 nop ff 1 2 no operation -------- 5pop a 0d 1 4 sp ? sp + 1, a ? m( sp ) 6pop x 2d 1 4 sp ? sp + 1, x ? m( sp ) -------- 7pop y 4d 1 4 sp ? sp + 1, y ? m( sp ) 8pop psw 6d 1 4 sp ? sp + 1, psw ? m( sp ) restored 9 push a 0e 1 4 m( sp ) ? a , sp ? sp - 1 10 push x 2e 1 4 m( sp ) ? x , sp ? sp - 1 -------- 11 push y 4e 1 4 m( sp ) ? y , sp ? sp - 1 12 push psw 6e 1 4 m( sp ) ? psw , sp ? sp - 1 13 ret 6f 1 5 return from subroutine sp ? sp +1, pc l ? m( sp ), sp ? sp +1, pc h ? m( sp ) -------- 14 reti 7f 1 6 return from interrupt sp ? sp +1, psw ? m( sp ), sp ? sp + 1, pc l ? m( sp ), sp ? sp + 1, pc h ? m( sp ) restored 15 stop ef 1 3 stop mode ( halt cpu, stop oscillator ) --------
c. mask order sheet mask order & verification sheet gms81c5108 1. customer information company name application order date yyyy tel: fax: name & signature: customer should write inside thick line box. 2. device information mm dd 3. marking specification 4. delivery schedule date quantity hynix confirmation yyyy mm dd yyyy mm dd customer sample risk order pcs pcs e-mail address: 5. rom code verification yyyy mm dd verification date: please confirm out verification data. check sum: tel: fax: name & signature: e-mail address: yyyy mm dd approval date: i agree with your verification data and confirm you to make mask set. tel: fax: name & signature: e-mail address: - ud fe b . 2001 gms81c5108-ud yyw w ko rea package 80qfp set 00 in this area 0000 h e000 h ffff h .otp file data dfff h mask data hitel chollian internet file name : ( .otp) check sum : ( ) osc option crystal r reset pull up yes no 8k rom size gms81c5108-ud yyw w korea customers area if the customer logo & part number must be used in this area, (please check mark into ) please submit a clean original logo & part number. hynix semiconductor inc.

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